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| ? 2003-2013 microchip technology inc. preliminary ds70091b-page 1 RFPIC12F675 high performance risc cpu: ? only 35 instructions to learn - all single cycle instructions except branches ? operating speed: - precision internal 4 mhz oscillator, factory calibrated to 1% - dc - 20 mhz resonator/crystal/clock modes - dc - 20 mhz crystal oscillator/clock input - dc - 4 mhz external rc oscillator - dc - 4 mhz xt crystal oscillator - external oscillator modes ? interrupt capability ? 8-level deep hardware stack ? direct, indirect and relative addressing modes peripheral features: ? memory - 1024 x 14 words of flash program memory - 128 x 8 bytes of eeprom data memory - 64 x 8 bytes of sram data memory - 100,000 write flash endurance - 1,000,000 write eeprom endurance - flash/data eeprom retention: > 40 years ? programmable code protection ? 6 i/o pins with individual direction control, weak pull-ups, and interrupt-on-pin change ? high current sink/source for direct led drive ? analog comparator: 16 internal reference levels ? analog-to-digital converter: 10 bits, 4 channels ? timer0: 8-bit timer/counter with 8-bit prescaler ? timer1: 16-bit timer/counter with 3-bit prescaler ? timer1 can use lp oscillator in intosc mode ?5 ? s wake-up from sleep typical with v dd = 3v ? in-circuit serial programming tm (icsp tm ) low power features: ? low power consumption: (typical with v dd = 3v) -14 ma transmitting +6 dbm at 434 mhz -4 ma transmitting -15 dbm at 434 mhz -500 ? a, 4.0 mhz intosc -0.6 ? a sleep with watchdog enabled -0.1 ? a standby current ? wide operating voltage range from 2.0 ? 5.5v ? industrial and extended temperature range pin diagram: uhf ask/fsk transmitter: ? integrated crystal oscillator, vco, loop filter and power amp for minimum external components ? ask data rate: 0 ? 40 kbps ? fsk data rate: 0 ? 40 kbps by crystal pulling ? output power: +10 dbm to -12 dbm in 4 steps ? adjustable transmitter power consumption ? transmit frequency set by crystal multiplied by 32 ? vco phase locked to quartz crystal reference; allows narrow band receivers to be used to maximize range and interference immunity ? crystal frequency divide by 4 available (refclk) ? used in applications conforming to us fcc part 15.231 and european en 300 220 regulations applications: ? automotive remote keyless entry (rke) systems ? automotive alarm systems ? community gate and garage door openers ? burglar alarm systems ? building access ? low power telemetry ? meter reading ? tire pressure sensors ? wireless sensors device frequency modulation RFPIC12F675k 290-350 mhz ask/fsk RFPIC12F675f 380-450 mhz ask/fsk RFPIC12F675h 850-930 mhz ask/fsk ssop v ss gp2/t0cki/int/cout data fsk gp1/cin-/icspclk v dd gp5/t1cki/osc1/clkin gp3/mclr /v pp rfen refclk ps v ddrf gp4/t1g /osc2/clkout data ask 2 3 4 5 6 7 8 9 ?1 19 18 16 15 14 13 12 17 20 RFPIC12F675k/f/h gp0/cin+/icspdat lf v ssrf v ssrf ant 10 11 fsk out rfxtal flash-based microcontroller with ask/fsk transmitter
RFPIC12F675 ds70091b-page 2 preliminary ? 2003-2013 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................... 3 2.0 memory organization......................................................................................................... ............................................................ 5 3.0 gpio port ................................................................................................................... ................................................................ 17 4.0 timer0 module............................................................................................................... ............................................................. 25 5.0 timer1 module with gate control ............................................................................................. .................................................. 28 6.0 comparator module ........................................................................................................... ......................................................... 33 7.0 analog-to-digital converter (a/d) module .................................................................................... .............................................. 39 8.0 data eeprom memory.......................................................................................................... .................................................... 45 9.0 uhf ask/fsk transmitter ..................................................................................................... .................................................... 49 10.0 special features of the cpu ................................................................................................ ...................................................... 55 11.0 instruction set summary .................................................................................................... ........................................................ 73 12.0 development support ........................................................................................................ ......................................................... 81 13.0 electrical specifications .................................................................................................. ............................................................ 87 14.0 dc and ac characteristics graphs and tables ................................................................................ ....................................... 113 15.0 packaging information ...................................................................................................... ........................................................ 123 appendix a: data sheet revision history........................................................................................ .................................................. 125 index ......................................................................................................................... ........................................................................ 127 on-line support................................................................................................................ ................................................................ 131 systems information and upgrade hot line ....................................................................................... .............................................. 131 reader response ................................................................................................................ ............................................................. 132 product identification system.................................................................................................. .......................................................... 133 to our valued customers it is our intention to provide our valued customers with the be st documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regardi ng this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) ? the microchip corporate literatu re center; u.s. fax: (480) 792-7277 when contacting a sales office or the literature center, pleas e specify which device, revision of silicon and data sheet (inclu de liter - ature number) you are using. customer notification system register on our web site at www.microchip.com/cn to receive the most current information on all of our products. ? 2003-2013 microchip technology inc. preliminary ds70091b-page 3 RFPIC12F675 1.0 device overview this document contains device specific information for the RFPIC12F675. additional information may be found in the picmicro tm mid-range reference manual (ds33023), which may be obtained from your local microchip sales representative or downloaded from the microchip web site. the reference manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. the RFPIC12F675 comes in a 20-pin ssop package. figure 1-1 shows a block diagram of the RFPIC12F675 device. ta b l e 1-1 shows the pinout description. figure 1-1: rfpic 12f675 block diagram flash program memory 1k x 14 13 data bus 8 14 program bus instruction reg program counter 8-level stack (13-bit) ram file registers 64 x 8 direct addr 7 addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control osc1/clkin osc2/clkout v dd , v ss 8 8 brown-out detect 8 3 timing generation gp5/t1cki/osc1/clkin internal 4 mhz ram gp4/an3/t1g /osc2/clkout gp3/mclr /v pp gp2/an2/t0cki/int/cout gp1/an1/cin-/v ref gp0/an0/cin+ oscillator note 1: higher order bits are from status register. analog timer0 timer1 data eeprom 128 bytes eedata eeaddr comparator analog to digital converter an0 an1 an2 an3 cin- cin+ cout t0cki t1cki v ref and reference t1g 8 clock divider voltage controlled oscillator rf power amplifier crystal oscillator phase/freq detector charge pump fsk switch refclk rf control logic fsk out v ddrf v ssrf v ssrf rfen ant lf rfxtal ps data ask divide by 32 data fsk RFPIC12F675 ds70091b-page 4 preliminary ? 2003-2013 microchip technology inc. table 1-1: RFPIC12F675 pinout pin buffer weak pull-up description in out 1v dd direct ? ? power supply 2 gp5 ttl cmos prog general purpose i/o. individually controlled interrupt-on-change. individually enabled pull-up. t1cki st ? ? timer1 clock osc1 xtal ? bias xtal connection clkin st ? ? external rc network or clock input 3 gp4 ttl cmos prog general purpose i/o. individually controlled interrupt-on-change. individually enabled pull-up. t1g st ? ? timer1 gate an3 analog ? ? a/d channel 3 input osc2 ? xtal bias xtal connection clkout ? cmos ? t osc /4 reference clock 4 gp3 ttl ? general purpose input. individually controlled interrupt-on- change. mclr st ? no master clear reset v pp hv ? ? programming voltage 5 rfxtal xtal xtal bias rf crystal 6 rfen ttl ? ? rf enable 7 refclk ? cmos ? reference clock/4 output (on RFPIC12F675k/f) reference clock/8 output (on RFPIC12F675h) 8 ps analog ? bias power select 9v ddrf direct ? ? rf power supply 10 v ssrf direct ? ? rf ground reference 11 ant ? od ? rf power amp output to antenna 12 v ssrf direct ? ? rf ground reference 13 lf analog analog ? loop filter 14 data ask ttl ? ? ask modulation data 15 data fsk ttl ? ? fsk modulation data 16 fsk out ? od ? fsk output to modulate reference crystal 17 gp2 st cmos prog general purpose i/o. individually controlled interrupt-on-change. individually enabled pull up. an2 analog ? ? a/d channel 2 input cout ? cmos ? comparator output t0cki st ? ? external clock for timer0 int st ? ? external interrupt 18 gp1 ttl cmos prog general purpose i/o. individually controlled interrupt-on-change. individually enabled pull-up. an1 analog ? ? a/d channel 1 input cin- analog ? ? comparator input - negative v ref analog ? ? external voltage reference icspclk st ? ? serial programming clock 19 gp0 ttl cmos prog general purpose i/o. individually controlled interrupt-on-change. individually enabled pull-up. an0 analog ? ? a/d channel 0 input cin+ analog ? ? comparator input - positive icspdat ttl cmos ? serial programming data i/o 20 v ss direct ? ? ground reference legend: ttl = ttl input buffer, st = schmitt trigger input buffer, od = open drain output ? 2003-2013 microchip technology inc. preliminary ds70091b-page 5 RFPIC12F675 2.0 memory organization 2.1 program memory organization the RFPIC12F675 devices have a 13-bit program coun - ter capable of addressing an 8k x 14 program memory space. only the first 1k x 14 (0000h - 03ffh) for the RFPIC12F675 devices is physically implemented. accessing a location above these boundaries will cause a wrap around within the first 1k x 14 space. the reset vector is at 0000h and the interrupt vector is at 0004h (see figure 2-1 ). figure 2-1: program memory map and stack for the RFPIC12F675 2.2 data memory organization the data memory (see figure 2-2 ) is partitioned into two banks, which contain the general purpose regis - ters and the special function registers. the special function registers are located in the first 32 locations of each bank. register locations 20h-5fh are general purpose registers, implemented as static ram and are mapped across both banks. all other ram is unimplemented and returns ?0? when read. rp0 (status<5>) is the bank select bit. ? rp0 = 0 bank 0 is selected ? rp0 = 1 bank 1 is selected 2.2.1 general purpose register file the register file is organized as 64 x 8 in the RFPIC12F675 devices. each register is accessed, either directly or indirectly, through the file select register fsr (see section 2.4 ). pc<12:0> 13 000h 0004 0005 03ffh 0400h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, return retfie, retlw stack level 2 note: the irp and rp1 bits status<7:6> are reserved and should always be maintained as ?0?s. RFPIC12F675 ds70091b-page 6 preliminary ? 2003-2013 microchip technology inc. 2.2.2 special function registers the special function registers are registers used by the cpu and peripheral functions for controlling the desired operation of the device (see tab l e 2-1 ). these registers are static ram. the special registers can be classified into two sets: core and peripheral. the special function registers associated with the ?core? are described in this section. those related to the operation of the peripheral features are described in the section of that peripheral feature. figure 2-2: data memory map of the RFPIC12F675 indirect addr. (1) tmr0 pcl status fsr gpio pclath intcon pir1 tmr1l tmr1h t1con 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 7fh bank 0 unimplemented data memory locations, read as '0'. 1: not a physical register. cmcon vrcon general purpose registers accesses 20h-5fh 64 bytes eedata eeadr eecon2 (1) 5fh 60h file address file address wpu ioc indirect addr. (1) option_reg pcl status fsr trisio pclath intcon pie1 pcon osccal 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh a0h ffh bank 1 dfh e0h adresh adcon0 eecon1 adresl ansel ? 2003-2013 microchip technology inc. preliminary ds70091b-page 7 RFPIC12F675 table 2-1: special function registers summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bod page bank 0 00h indf (1) addressing this location uses contents of fsr to address data memory 0000 0000 16 , 63 01h tmr0 timer0 module?s register xxxx xxxx 25 02h pcl program counter's (pc) least significant byte 0000 0000 15 03h status irp (2) rp1 (2) rp0 to pd z dc c 0001 1xxx 9 04h fsr indirect data memory address pointer xxxx xxxx 16 05h gpio ? ? gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 --xx xxxx 17 06h ? unimplemented ? ? 07h ? unimplemented ? ? 08h ? unimplemented ? ? 09h ? unimplemented ? ? 0ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 15 0bh intcon gie peie t0ie inte gpie t0if intf gpif 0000 0000 11 0ch pir1 eeif adif ? ? cmif ? ? tmr1if 00-- 0--0 13 0dh ? unimplemented ? ? 0eh tmr1l holding register for the least significant byte of the 16-bit timer1 xxxx xxxx 28 0fh tmr1h holding register for the most significant byte of the 16-bit timer1 xxxx xxxx 28 10h t1con ? tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on -000 0000 30 11h ? unimplemented ? ? 12h ? unimplemented ? ? 13h ? unimplemented ? ? 14h ? unimplemented ? ? 15h ? unimplemented ? ? 16h ? unimplemented ? ? 17h ? unimplemented ? ? 18h ? unimplemented ? ? 19h cmcon ? cout ? cinv cis cm2 cm1 cm0 -0-0 0000 33 1ah ? unimplemented ? ? 1bh ? unimplemented ? ? 1ch ? unimplemented ? ? 1dh ? unimplemented ? ? 1eh adresh most significant 8 bits of the left shifted a/ d result or 2 bits of the right shifted result xxxx xxxx 40 1fh adcon0 adfm vcfg ? ? chs1 chs0 go/ done adon 00-- 0000 41 , 63 legend: ? = unimplemented locations read as ?0?, u = unchanged, x = unknown, q = value depends on condition, ? shaded = unimplemented note 1: this is not a physical register. 2: these bits are reserved and should always be maintained as ?0?. RFPIC12F675 ds70091b-page 8 preliminary ? 2003-2013 microchip technology inc. bank 1 80h indf (1) addressing this location uses contents of fsr to address data memory 0000 0000 16 , 63 81h option_reg gppu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 10 , 26 82h pcl program counter's (pc) least significant byte 0000 0000 15 83h status irp (2) rp1 (2) rp0 to pd z dc c 0001 1xxx 9 84h fsr indirect data memory address pointer xxxx xxxx 16 85h trisio ? ? trisio5 trisio4 trisio3 trisio2 trisio1 trisio0 --11 1111 17 86h ? unimplemented ? ? 87h ? unimplemented ? ? 88h ? unimplemented ? ? 89h ? unimplemented ? ? 8ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 15 8bh intcon gie peie t0ie inte gpie t0if intf gpif 0000 0000 11 8ch pie1 eeie adie ? ? cmie ? ? tmr1ie 00-- 0--0 12 8dh ? unimplemented ? ? 8eh pcon ? ? ? ? ? ? por bod ---- --0x 14 8fh ? unimplemented ? ? 90h osccal cal5 cal4 cal3 cal2 cal1 cal0 ? ? 1000 00-- 14 91h ? unimplemented ? ? 92h ? unimplemented ? ? 93h ? unimplemented ? ? 94h ? unimplemented ? ? 95h wpu ? ? wpu5 wpu4 ? wpu2 wpu1 wpu0 --11 -111 18 96h ioc ? ? ioc5 ioc4 ioc3 ioc2 ioc1 ioc0 --00 0000 19 97h ? unimplemented ? ? 98h ? unimplemented ? ? 99h vrcon vren ? vrr ? vr3 vr2 vr1 vr0 0-0- 0000 38 9ah eedata data eeprom data register 0000 0000 45 9bh eeadr ? data eeprom address register -000 0000 45 9ch eecon1 ? ? ? ? wrerr wren wr rd ---- x000 46 9dh eecon2 (1) eeprom control register 2 ---- ---- 46 9eh adresl least significant 2 bits of the left shifted a/d result of 8 bits or the right shifted result xxxx xxxx 40 9fh ansel ? adcs2 adcs1 adcs0 ans3 ans2 ans1 ans0 -000 1111 42 , 63 legend: ? = unimplemented locations read as ?0?, u = unchanged, x = unknown, q = value depends on condition, ? shaded = unimplemented note 1: this is not a physical register. 2: these bits are reserved and should always be maintained as ?0?. table 2-1: special function registers summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bod page ? 2003-2013 microchip technology inc. preliminary ds70091b-page 9 RFPIC12F675 2.2.2.1 status register the status register, shown in register 2-1 , contains: ? the arithmetic status of the alu ? the reset status ? the bank select bits for data memory (sram) the status register can be the destination for any instruction, like any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect any status bits. for other instructions not affecting any status bits, see the ?instruction set summary?. register 2-1: status ? status register (address: 03h or 83h) note 1: bits irp and rp1 (status<7:6>) are not used by the RFPIC12F675 and should be maintained as clear. use of these bits is not recommended, since this may affect upward compatibility with future products. 2: the c and dc bits operate as a borrow and digit borrow out bit, respectively, in subtraction. see the sublw and subwf instructions for examples. reserved reserved r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd z dc c bit 7 bit 0 bit 7 irp: this bit is reserved and should be maintained as ?0? bit 6 rp1: this bit is reserved and should be maintained as ?0? bit 5 rp0: register bank select bit (used for direct addressing) ? 1 = bank 1 (80h - ffh) 0 = bank 0 (00h - 7fh) bit 4 to : time-out bit ? 1 = after power-up, clrwdt instruction, or sleep instruction ? 0 = a wdt time-out occurred bit 3 pd : power-down bit ? 1 = after power-up or by the clrwdt instruction ? 0 = by execution of the sleep instruction bit 2 z : zero bit ? 1 = the result of an arithmetic or logic operation is zero ? 0 = the result of an arithmetic or logic operation is not zero bit 1 dc : digit carry/ borrow bit ( addwf , addlw,sublw,subwf instructions) ? for borrow, the polarity is reversed. ? 1 = a carry-out from the 4th low order bit of the result occurred ? 0 = no carry-out from the 4th low order bit of the result bit 0 c : carry/ borrow bit ( addwf , addlw, sublw, subwf instructions) ? 1 = a carry-out from the most significant bit of the result occurred ? 0 = no carry-out from the most significant bit of the result occurred note: for borrow the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low order bit of the source register legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown RFPIC12F675 ds70091b-page 10 preliminary ? 2003-2013 microchip technology inc. 2.2.2.2 option register the option register is a readable and writable register, which contains various control bits to configure: ? tmr0/wdt prescaler ? external gp2/int interrupt ?tmr0 ? weak pull-ups on gpio register 2-2: option_reg ? option register (address: 81h) note: to achieve a 1:1 prescaler assignment for tmr0, assign the prescaler to the wdt by setting psa bit to ?1? (option<3>). see section 4.4 . r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 gppu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 bit 7 gppu : gpio pull-up enable bit ? 1 = gpio pull-ups are disabled ? 0 = gpio pull-ups are enabled by individual port latch values bit 6 intedg: interrupt edge select bit ? 1 = interrupt on rising edge of gp2/int pin ? 0 = interrupt on falling edge of gp2/int pin bit 5 t0cs: tmr0 clock source select bit ? 1 = transition on gp2/t0cki pin ? 0 = internal instruction cycle clock (clkout) bit 4 t0se: tmr0 source edge select bit ? 1 = increment on high-to-low transition on gp2/t0cki pin ? 0 = increment on low-to-high transition on gp2/t0cki pin bit 3 psa: prescaler assignment bit ? 1 = prescaler is assigned to the wdt ? 0 = prescaler is assigned to the timer0 module bit 2-0 ps2:ps0: prescaler rate select bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate ? 2003-2013 microchip technology inc. preliminary ds70091b-page 11 RFPIC12F675 2.2.2.3 intcon register the intcon register is a readable and writable register, which contains the various enable and flag bits for tmr0 register overflow, gpio port change and external gp2/int pin interrupts. register 2-3: intcon ? interrupt control register (address: 0bh or 8bh) note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gie peie t0ie inte gpie t0if intf gpif bit 7 bit 0 bit 7 gie: global interrupt enable bit ? 1 = enables all unmasked interrupts ? 0 = disables all interrupts bit 6 peie: peripheral interrupt enable bit ? 1 = enables all unmasked peripheral interrupts ? 0 = disables all peripheral interrupts bit 5 t0ie: tmr0 overflow interrupt enable bit ? 1 = enables the tmr0 interrupt ? 0 = disables the tmr0 interrupt bit 4 inte: gp2/int external interrupt enable bit ? 1 = enables the gp2/int external interrupt ? 0 = disables the gp2/int external interrupt bit 3 gpie: port change interrupt enable bit (1) ? 1 = enables the gpio port change interrupt ? 0 = disables the gpio port change interrupt bit 2 t0if: tmr0 overflow interrupt flag bit (2) ? 1 = tmr0 register has overflowed (must be cleared in software) ? 0 = tmr0 register did not overflow bit 1 intf: gp2/int external interrupt flag bit ? 1 = the gp2/int external interrupt occurred (must be cleared in software) ? 0 = the gp2/int external interrupt did not occur bit 0 gpif: port change interrupt flag bit ? 1 = when at least one of the gp5:gp0 pins changed state (must be cleared in software) ? 0 = none of the gp5:gp0 pins have changed state ? note 1: ioc register must also be enabled to enable an interrupt-on-change. 2: t0if bit is set when timer0 rolls over. timer0 is unchanged on reset and should be initialized before clearing t0if bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown RFPIC12F675 ds70091b-page 12 preliminary ? 2003-2013 microchip technology inc. 2.2.2.4 pie1 register the pie1 register contains the interrupt enable bits, as shown in register 2-4 . register 2-4: pie1 ? peripheral interrupt enable register 1 (address: 8ch) note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. r/w-0 r/w-0 u-0 u-0 r/w-0 u-0 u-0 r/w-0 eeie adie ? ? cmie ? ? tmr1ie bit 7 bit 0 bit 7 eeie: ee write complete interrupt enable bit ? 1 = enables the ee write complete interrupt ? 0 = disables the ee write complete interrupt bit 6 adie: a/d converter interrupt enable bit ? 1 = enables the a/d converter interrupt ? 0 = disables the a/d converter interrupt bit 5-4 unimplemented: read as ?0? bit 3 cmie: comparator interrupt enable bit ? 1 = enables the comparator interrupt ? 0 = disables the comparator interrupt bit 2-1 unimplemented: read as ?0? bit 0 tmr1ie: tmr1 overflow interrupt enable bit ? 1 = enables the tmr1 overflow interrupt ? 0 = disables the tmr1 overflow interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2003-2013 microchip technology inc. preliminary ds70091b-page 13 RFPIC12F675 2.2.2.5 pir1 register the pir1 register contains the interrupt flag bits, as shown in register 2-5 . register 2-5: pir1 ? peripheral interrupt register 1 (address: 0ch) note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 u-0 u-0 r/w-0 u-0 u-0 r/w-0 eeif adif ? ? cmif ? ? tmr1if bit 7 bit 0 bit 7 eeif: eeprom write operation interrupt flag bit ? 1 = the write operation completed (must be cleared in software) ? 0 = the write operation has not completed or has not been started bit 6 adif: a/d converter interrupt flag bit ? 1 = the a/d conversion is complete (must be cleared in software) ? 0 = the a/d conversion is not complete bit 5-4 unimplemented : read as ?0? bit 3 cmif : comparator interrupt flag bit ? 1 = comparator input has changed (must be cleared in software) ? 0 = comparator input has not changed bit 2-1 unimplemented : read as ?0? bit 0 tmr1if : tmr1 overflow interrupt flag bit ? 1 = tmr1 register overflowed (must be cleared in software) ? 0 = tmr1 register did not overflow legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown RFPIC12F675 ds70091b-page 14 preliminary ? 2003-2013 microchip technology inc. 2.2.2.6 pcon register the power control (pcon) register contains flag bits to differentiate between a: ? power-on reset (por) ? brown-out detect (bod) ? watchdog timer reset (wdt) ?external mclr reset the pcon register bits are shown in register 2-6 . register 2-6: pcon ? power control register (address: 8eh) 2.2.2.7 osccal register the oscillator calibration register (osccal) is used to calibrate the internal 4 mhz oscillator. it contains 6 bits to adjust the frequency up or down to achieve 4 mhz. the osccal register bits are shown in register 2-7 . register 2-7: osccal ? oscillator calibration register (address: 90h) u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-x ? ? ? ? ? ? por bod bit 7 bit 0 bit 7-2 unimplemented: read as '0' bit 1 por : power-on reset status bit ? 1 = no power-on reset occurred ? 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bod : brown-out detect status bit ? 1 = no brown-out detect occurred ? 0 = a brown-out detect occurred (must be set in software after a brown-out detect occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 cal5 cal4 cal3 cal2 cal1 cal0 ? ? bit 7 bit 0 bit 7-2 cal5:cal0: 6-bit signed oscillator calibration bits ? 111111 = maximum frequency ? 100000 = center frequency ? 000000 = minimum frequency bit 1-0 unimplemented: read as '0' legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2003-2013 microchip technology inc. preliminary ds70091b-page 15 RFPIC12F675 2.3 pcl and pclath the program counter (pc) is 13-bits wide. the low byte comes from the pcl register, which is a readable and writable register. the high byte (pc<12:8>) is not directly readable or writable and comes from pclath. on any reset, the pc is cleared. figure 2-3 shows the two situations for the loading of the pc. the upper example in figure 2-3 shows how the pc is loaded on a write to pcl (pclath<4:0> ? pch). the lower example in figure 2-3 shows how the pc is loaded during a call or goto instruction (pclath<4:3> ? pch). figure 2-3: loading of pc in different situations 2.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when perform - ing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). refer to the application note ?implementing a table read" (an556). 2.3.2 stack the RFPIC12F675 family has an 8-level deep x 13-bit wide hardware stack (see figure 2-1 ). the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed, or an interrupt causes a branch. the stack is poped in the event of a return, retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu result goto, call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl pcl as destination note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call, return, retlw and retfie instructions, or the vectoring to an interrupt address. RFPIC12F675 ds70091b-page 16 preliminary ? 2003-2013 microchip technology inc. 2.4 indirect addressing, indf and fsr registers the indf register is not a physical register. addressing the indf register will cause indirect addressing. indirect addressing is possible by using the indf register. any instruction using the indf register actu - ally accesses data pointed to by the file select register (fsr). reading indf itself indirectly will produce 00h. writing to the indf register indirectly results in a no operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 2-4 . a simple program to clear ram location 20h-2fh using indirect addressing is shown in example 2-1 . example 2-1: indirect addressing figure 2-4: direct/indirect addressing RFPIC12F675 movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr ;inc pointer btfss fsr,4 ;all done? goto next ;no clear next continue ;yes continue for memory map detail see figure 2-2. note 1: the rp1 and irp bits are reserved; always maintain these bits clear. data memory indirect addressing direct addressing bank select location select rp1 (1) rp0 6 0 from opcode irp (1) fsr register 7 0 bank select location select 00 01 10 11 180h 1ffh 00h 7fh bank 0 bank 1 bank 2 bank 3 not used ? 2003-2013 microchip technology inc. preliminary ds70091b-page 17 RFPIC12F675 3.0 gpio port there are as many as six general purpose i/o pins available. depending on which peripherals are enabled, some or all of the pins may not be available as general purpose i/o. in general, when a peripheral is enabled, the associated pin may not be used as a general purpose i/o pin. 3.1 gpio and the trisio registers gpio is an 6-bit wide, bi-directional port. the corresponding data direction register is trisio. setting a trisio bit (= 1) will make the corresponding gpio pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisio bit (= 0) will make the corresponding gpio pin an output (i.e., put the contents of the output latch on the selected pin). the exception is gp3, which is input only and its trisio bit will always read as ?1?. example 3-1 shows how to initialize gpio. reading the gpio register reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. there - fore, a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. gp3 reads ?0? when mclren = 1. the trisio register controls the direction of the gp pins, even when they are being used as analog inputs. the user must ensure the bits in the trisio register are maintained set when using them as analog inputs. i/o pins configured as analog inputs always read ?0?. example 3-1: initializing gpio 3.2 additional pin functions every gpio pin on the RFPIC12F675 has an interrupt- on-change option and every gpio pin, except gp3, has a weak pull-up option. the next two sections describe these functions. 3.2.1 weak pull-up each of the gpio pins, except gp3, has an individually configurable weak internal pull-up. control bits wpux enable or disable each pull-up. refer to register 3-3 . each weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset by the gppu bit (option<7>). register 3-1: gpio ? gpio regi ster (address: 05h) note: additional information on i/o ports may be found in the pic mid-range reference manual (ds33023) note: the ansel (9fh) and cmcon (19h) registers (9fh) must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ?0?. bcf status,rp0 ;bank 0 clrf gpio ;init gpio movlw 07h ;set gp<2:0> to movwf cmcon ;digital io bsf status,rp0 ;bank 1 clrf ansel ;digital i/o movlw 0ch ;set gp<3:2> as inputs movwf trisio ;and set gp<5:4,1:0> ;as outputs u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 bit 7 bit 0 bit 7-6: unimplemented : read as ?0? bit 5-0: gpio<5:0> : general purpose i/o pin. 1 = port pin is >v ih 0 = port pin is ? 2003-2013 microchip technology inc. preliminary ds70091b-page 19 RFPIC12F675 3.2.2 interrupt-on-change each of the gpio pins is individually configurable as an interrupt-on-change pin. control bits ioc enable or disable the interrupt function for each pin. refer to register 3-4 . the interrupt-on-change is disabled on a power-on reset. for enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of gpio. the ?mismatch? outputs of the last read are or'd together to set, the gp port change interrupt flag bit (gpif) in the intcon register. this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of gpio. this will end the mismatch condition. b) clear the flag bit gpif. a mismatch condition will continue to set flag bit gpif. reading gpio will end the mismatch condition and allow flag bit gpif to be cleared. register 3-4: ioc ? interrupt-on-chang e gpio register (address: 96h) note: if a change on the i/o pin should occur when the read operation is being executed (start of the q2 cycle), then the gpif inter - rupt flag may not get set. u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ioc5 ioc4 ioc3 ioc2 ioc1 ioc0 bit 7 bit 0 bit 7-6 unimplemented: read as ?0? bit 5-0 ioc<5:0>: interrupt-on-change gpio control bit ? 1 = interrupt-on-change enabled ? 0 = interrupt-on-change disabled ? note 1: global interrupt enable (gie) must be enabled for individual interrupts to be recognized. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown RFPIC12F675 ds70091b-page 20 preliminary ? 2003-2013 microchip technology inc. 3.3 pin descriptions and diagrams each gpio pin is multiplexed with other functions. the pins and their combined functions are briefly described here. for specific information about individual functions such as the comparator or the a/d, refer to the appropriate section in this data sheet. 3.3.1 gp0/an0/cin+ figure 3-1 shows the diagram for this pin. the gp0 pin is configurable to function as one of the following: ? a general purpose i/o ? an analog input for the a/d ? an analog input to the comparator 3.3.2 gp1/an1/cin-/v ref figure 3-1 shows the diagram for this pin. the gp1 pin is configurable to function as one of the following: ? as a general purpose i/o ? an analog input for the a/d ? an analog input to the comparator ? a voltage reference input for the a/d figure 3-1: block diagram of gp0 and gp1 pins i/o pin v dd v ss d q ck q d q ck q d q ck q d q ck q v dd d en q d en q weak data bus wr wpu rd wpu rd port rd port wr port wr trisio rd trisio wr ioc rd ioc interrupt-on-change to comparator to a/d converter analog input mode gppu analog input mode ? 2003-2013 microchip technology inc. preliminary ds70091b-page 21 RFPIC12F675 3.3.3 gp2/an2/t0cki/int/cout figure 3-2 shows the diagram for this pin. the gp2 pin is configurable to function as one of the following: ? a general purpose i/o ? an analog input for the a/d ? the clock input for tmr0 ? an external edge triggered interrupt ? a digital output from the comparator figure 3-2: block diagram of gp2 3.3.4 gp3/ mclr /v pp figure 3-3 shows the diagram for this pin. the gp3 pin is configurable to function as one of the following: ? a general purpose input ? as master clear reset figure 3-3: block diagram of gp3 i/o pin v dd v ss d q ck q d q ck q d q ck q d q ck q v dd d en q d en q weak analog input mode data bus wr wpu rd wpu rd port wr port wr trisio rd trisio wr ioc rd ioc interrupt-on-change to a/d converter 0 1 cout cout enable to i n t to t m r 0 analog input mode gppu rd port analog input mode i/o pin v ss d q ck q d en q data bus rd port rd port wr ioc rd ioc interrupt-on-change reset mclre rd trisio v ss d en q mclre RFPIC12F675 ds70091b-page 22 preliminary ? 2003-2013 microchip technology inc. 3.3.5 gp4/an3/ t1g /osc2/clkout figure 3-4 shows the diagram for this pin. the gp4 pin is configurable to function as one of the following: ? a general purpose i/o ? an analog input for the a/d ? a tmr1 gate input ? a crystal/resonator connection ? a clock output figure 3-4: block diagram of gp4 3.3.6 gp5/t1cki/osc1/clkin figure 3-5 shows the diagram for this pin. the gp5 pin is configurable to function as one of the following: ? a general purpose i/o ?a tmr1 clock input ? a crystal/resonator connection ? a clock input figure 3-5: block diagram of gp5 i/o pin v dd v ss d q ck q d q ck q d q ck q d q ck q v dd d en q d en q weak analog input mode data bus wr wpu rd wpu rd port wr port wr trisio rd trisio wr ioc rd ioc interrupt-on-change f osc /4 to a/d converter oscillator circuit osc1 clkout 0 1 clkout enable enable analog input mode gppu rd port to t m r 1 t 1 g intosc/ rc/ec (2) clk modes (1) clkout enable note 1: clk modes are xt, hs, lp, lptmr1 and clkout enable. 2: with clkout option. i/o pin v dd v ss d q ck q d q ck q d q ck q d q ck q v dd d en q d en q weak data bus wr wpu rd wpu rd port wr port wr trisio rd trisio wr ioc rd ioc interrupt-on-change to tmr1 or clkgen intosc mode rd port intosc mode gppu oscillator circuit osc2 note 1: timer1 lp oscillator enabled 2: when using timer1 with lp oscillator, the schmitt trigger is by-passed. (2) tmr1lpen (1) ? 2003-2013 microchip technology inc. preliminary ds70091b-page 23 RFPIC12F675 table 3-1: summary of registers associated with gpio address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bod value on all other resets 05h gpio ? ? gp5 gp4 gp3 gp2 gp1 gp0 --xx xxxx --uu uuuu 0bh/8bh intcon gie peie t0ie inte gpie t0if intf gpif 0000 0000 0000 000u 19h cmcon ? cout ? cinv cis cm2 cm1 cm0 -0-0 0000 -0-0 0000 81h option_reg gppu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisio ? ? trisio5 trisio4 trisio3 trisio2 trisio1 trisio0 --11 1111 --11 1111 95h wpu ? ? wpu5 wpu4 ? wpu2 wpu1 wpu0 --11 -111 --11 -111 96h ioc ? ? ioc5 ioc4 ioc3 ioc2 ioc1 ioc0 --00 0000 --00 0000 9fh ansel ? adcs2 adcs1 adcs0 ans3 ans2 ans1 ans0 -000 1111 -000 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0 '. shaded cells are not used by gpio. RFPIC12F675 ds70091b-page 24 preliminary ? 2003-2013 microchip technology inc. notes: ? 2003-2013 microchip technology inc. preliminary ds70091b-page 25 RFPIC12F675 4.0 timer0 module the timer0 module timer/counter has the following features: ? 8-bit timer/counter ? readable and writable ? 8-bit software programmable prescaler ? internal or external clock select ? interrupt on overflow from ffh to 00h ? edge select for external clock figure 4-1 is a block diagram of the timer0 module and the prescaler shared with the wdt. 4.1 timer0 operation timer mode is selected by clearing the t0cs bit (option_reg<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if tmr0 is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit (option_reg<5>). in this mode, the timer0 module will increment either on every rising or falling edge of pin gp2/t0cki. the incrementing edge is determined by the source edge (t0se) control bit (option_reg<4>). clearing the t0se bit selects the rising edge. 4.2 timer0 interrupt a timer0 interrupt is generated when the tmr0 register timer/counter overflows from ffh to 00h. this overflow sets the t0if bit. the interrupt can be masked by clearing the t0ie bit (intcon<5>). the t0if bit (intcon<2>) must be cleared in software by the timer0 module interrupt service routine before re- enabling this interrupt. the timer0 interrupt cannot wake the processor from sleep since the timer is shut-off during sleep. figure 4-1: block di agram of the timer0/wdt prescaler note: additional information on the timer0 module is available in the picmicro tm mid- range reference manual (ds33023). note: counter mode has specific external clock requirements. additional information on these requirements is available in the picmicro tm mid-range reference manual (ds33023). t0cki t0se pin clkout tmr0 watchdog timer wdt time-out ps0 - ps2 wdte data bus set flag bit t0if on overflow t0cs note 1: t0se, t0cs, psa, ps0-ps2 are bits in the option register. 0 1 0 1 0 1 sync 2 cycles 8 8 8-bit prescaler 0 1 (= f osc /4) psa psa psa RFPIC12F675 ds70091b-page 26 preliminary ? 2003-2013 microchip technology inc. 4.3 using timer0 with an external clock when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki, with the internal phase clocks, is accom - plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks. therefore, it is necessary for t0cki to be high for at least 2t osc (and a small rc delay of 20 ns) and low for at least 2t osc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. register 4-1: option_reg ? option register (address: 81h) note: the ansel (9fh) and cmcon (19h) registers must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ?0?. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 gppu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 bit 7 gppu : gpio pull-up enable bit ? 1 = gpio pull-ups are disabled ? 0 = gpio pull-ups are enabled by individual port latch values bit 6 intedg: interrupt edge select bit ? 1 = interrupt on rising edge of gp2/int pin ? 0 = interrupt on falling edge of gp2/int pin bit 5 t0cs: tmr0 clock source select bit ? 1 = transition on gp2/t0cki pin ? 0 = internal instruction cycle clock (clkout) bit 4 t0se: tmr0 source edge select bit ? 1 = increment on high-to-low transition on gp2/t0cki pin ? 0 = increment on low-to-high transition on gp2/t0cki pin bit 3 psa: prescaler assignment bit ? 1 = prescaler is assigned to the wdt ? 0 = prescaler is assigned to the timer0 module bit 2-0 ps2:ps0: prescaler rate select bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate ? 2003-2013 microchip technology inc. preliminary ds70091b-page 27 RFPIC12F675 4.4 prescaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer. for simplicity, this counter will be referred to as ?prescaler? throughout this data sheet. the prescaler assignment is controlled in software by the control bit psa (option_reg<3>). clearing the psa bit will assign the prescaler to timer0. prescale values are selectable via the ps2:ps0 bits (option_reg<2:0>). the prescaler is not readable or writable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1, x....etc. ) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. 4.4.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed ?on the fly? during program execution). to avoid an unintended device reset, the following instruction sequence ( example 4-1 ) must be executed when changing the prescaler assignment from timer0 to wdt. example 4-1: changing prescaler (timer0 ? wdt) to change prescaler from the wdt to the tmr0 module, use the sequence shown in example 4-2 . this precaution must be taken even if the wdt is disabled. example 4-2: changing prescaler (wdt ? timer0) table 4-1: registers associated with timer0 bcf status,rp0 ;bank 0 clrwdt ;clear wdt clrf tmr0 ;clear tmr0 and ; prescaler bsf status,rp0 ;bank 1 movlw b?00101111? ;required if desired movwf option_reg ; ps2:ps0 is clrwdt ; 000 or 001 ; movlw b?00101xxx? ;set postscaler to movwf option_reg ; desired wdt rate bcf status,rp0 ;bank 0 clrwdt ;clear wdt and ; postscaler bsf status,rp0 ;bank 1 movlw b?xxxx0xxx? ;select tmr0, ; prescale, and ; clock source movwf option_reg ; bcf status,rp0 ;bank 0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bod value on all other resets 01h tmr0 timer0 module register xxxx xxxx uuuu uuuu 0bh/8bh intcon gie peie t0ie inte gpie t0if intf gpif 0000 0000 0000 000u 81h option_reg gppu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisio ? ? trisio5 trisio4 trisio3 trisio2 trisio1 trisio0 --11 1111 --11 1111 legend: ? = unimplemented locations, read as ?0?, u = unchanged, x = unknown. ? shaded cells are not used by the timer0 module. RFPIC12F675 ds70091b-page 28 preliminary ? 2003-2013 microchip technology inc. 5.0 timer1 module with gate control the RFPIC12F675 devices have a 16-bit timer. figure 5-1 shows the basic block diagram of the timer1 module. timer1 has the following features: ? 16-bit timer/counter (tmr1h:tmr1l) ? readable and writable ? internal or external clock selection ? synchronous or asynchronous operation ? interrupt on overflow from ffffh to 0000h ? wake-up upon overflow (asynchronous mode) ? optional external enable input ( t1g ) ? optional lp oscillator the timer1 control register (t1con), shown in register 5-1 , is used to enable/disable timer1 and select the various features of the timer1 module. figure 5-1: timer1 block diagram note: additional information on timer modules is available in the picmicro tm mid-range reference manual (ds33023). tmr1h tmr1l lp oscillator t1sync tmr1cs t1ckps<1:0> sleep input f osc /4 internal clock prescaler 1, 2, 4, 8 synchronize detect 1 0 0 1 synchronized clock input 2 osc1 osc2 set flag bit tmr1if on overflow tmr1 tmr1on tmr1ge tmr1on tmr1ge intosc t1oscen lp w/o clkout t1g ? 2003-2013 microchip technology inc. preliminary ds70091b-page 29 RFPIC12F675 5.1 timer1 modes of operation timer1 can operate in one of three modes: ? 16-bit timer with prescaler ? 16-bit synchronous counter ? 16-bit asynchronous counter in timer mode, timer1 is incremented on every instruction cycle. in counter mode, timer1 is incremented on the rising edge of the external clock input t1cki. in addition, the counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. in counter and timer modules, the counter/timer clock can be gated by the t1g input. if an external clock oscillator is needed (and the microcontroller is using the intosc w/o clkout), timer1 can use the lp oscillator as a clock source. 5.2 timer1 interrupt the timer1 register pair (tmr1h:tmr1l) increments to ffffh and rolls over to 0000h. when timer1 rolls over, the timer1 interrupt flag bit (pir1<0>) is set. to enable the interrupt on rollover, you must set these bits: ? timer1 interrupt enable bit (pie1<0>) ? peie bit (intcon<6>) ? gie bit (intcon<7>). the interrupt is cleared by clearing the tmr1if in the interrupt service routine. 5.3 timer1 prescaler timer1 has four prescaler options allowing 1, 2, 4, or 8 divisions of the clock input. the t1ckps bits (t1con<5:4>) control the prescale counter. the prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to tmr1h or tmr1l. figure 5-2: timer1 incrementing edge note: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge. note: the tmr1h:ttmr1l register pair and the tmr1if bit should be cleared before enabling interrupts. t1cki = 1 when tmr1 enabled t1cki = 0 when tmr1 enabled note 1: arrows indicate counter increments. 2: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. RFPIC12F675 ds70091b-page 30 preliminary ? 2003-2013 microchip technology inc. register 5-1: t1con ? timer1 co ntrol register (address: 10h) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 bit 7 unimplemented: read as ?0? bit 6 tmr1ge: timer1 gate enable bit ? if tmr1on = 0: ? this bit is ignored if tmr1on = 1: ? 1 = timer1 is on if t1g pin is low ? 0 = timer1 is on bit 5-4 t1ckps1:t1ckps0: timer1 input clock prescale select bits ? 11 = 1:8 prescale value ? 10 = 1:4 prescale value ? 01 = 1:2 prescale value ? 00 = 1:1 prescale value bit 3 t1oscen: lp oscillator enable control bit ? if intosc without clkout oscillator is active: ? 1 = lp oscillator is enabled for timer1 clock ? 0 = lp oscillator is off else: ? this bit is ignored bit 2 t1sync : timer1 external clock input synchronization control bit ? tmr1cs = 1: ? 1 = do not synchronize external clock input ? 0 = synchronize external clock input tmr1cs = 0: this bit is ignored. timer1 uses the internal clock. bit 1 tmr1cs: timer1 clock source select bit ? 1 = external clock from t1oso/t1cki pin (on the rising edge) ? 0 = internal clock (f osc /4) bit 0 tmr1on: timer1 on bit ? 1 = enables timer1 ? 0 = stops timer1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2003-2013 microchip technology inc. preliminary ds70091b-page 31 RFPIC12F675 5.4 timer1 operation in asynchronous counter mode if control bit t1sync (t1con<2>) is set, the external clock input is not synchronized. the timer continues to increment asynchronous to the internal phase clocks. the timer will continue to run during sleep and can generate an interrupt on overflow, which will wake-up the processor. however, special precautions in software are needed to read/write the timer ( section 5.4.1 ). 5.4.1 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l, while the timer is running from an external asynchronous clock, will ensure a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write contention may occur by writing to the timer registers, while the register is incrementing. this may produce an unpredictable value in the timer register. reading the 16-bit value requires some care. examples 12-2 and 12-3 in the pic mid-range mcu family reference manual (ds33023) show how to read and write timer1 when it is running in asynchronous mode. 5.5 timer1 oscillator a crystal oscillator circuit is built-in between pins osc1 (input) and osc2 (amplifier output). it is enabled by setting control bit t1oscen (t1con<3>). the oscillator is a low power oscillator rated up to 37 khz. it will continue to run during sleep. it is primarily intended for a 32 khz crystal. ta b l e 10-2 shows the capacitor selection for the timer1 oscillator. the timer1 oscillator is shared with the system lp oscillator. thus, timer1 can use this mode only when the system clock is derived from the internal oscillator. as with the system lp oscillator, the user must provide a software time delay to ensure proper oscillator start-up. while enabled, trisio4 and trisio5 are set. gp4 and gp5 read ?0? and trisio4 and trisio5 are read ?1?. 5.6 timer1 operation during sleep timer1 can only operate during sleep when setup in asynchronous counter mode. in this mode, an external crystal or clock source can be used to increment the counter. to setup the timer to wake the device: ? timer1 must be on (t1con<0>) ? tmr1ie bit (pie1<0>) must be set ? peie bit (intcon<6>) must be set the device will wake-up on an overflow. if the gie bit (intcon<7>) is set, the device will wake-up and jump to the interrupt service routine on an overflow. table 5-1: registers associated with timer1 as a timer/counter note: the ansel (9fh) and cmcon (19h) registers must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ?0?. note: the oscillator requires a start-up and stabilization time before use. thus, t1oscen should be set and a suitable delay observed prior to enabling timer1. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bod value on all other resets 0bh/8bh intcon gie peie t0ie inte gpie t0if intf gpif 0000 0000 0000 000u 0ch pir1 eeif adif ? ? cmif ? ? tmr1if 00-- 0--0 00-- 0--0 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on -000 0000 -uuu uuuu 8ch pie1 eeie adie ? ? cmie ? ? tmr1ie 00-- 0--0 00-- 0--0 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by the timer1 module. RFPIC12F675 ds70091b-page 32 preliminary ? 2003-2013 microchip technology inc. notes: ? 2003-2013 microchip technology inc. preliminary ds70091b-page 33 RFPIC12F675 6.0 comparator module the RFPIC12F675 devices have one analog comparator. the inputs to the comparator are multiplexed with the gp0 and gp1 pins. there is an on-chip comparator voltage reference that can also be applied to an input of the comparator. in addition, gp2 can be configured as the comparator output. the comparator control register (cmcon), shown in register 6-1 , contains the bits to control the comparator. register 6-1: cmcon ? comparator control register (address: 19h) u-0 r-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? cout ? cinv cis cm2 cm1 cm0 bit 7 bit 0 bit 7 unimplemented : read as ?0? bit 6 cout : comparator output bit when c i nv = 0: ? 1 = v in + > v in - ? 0 = v in + < v in - when c i nv = 1: ? 1 = v in + < v in - 0 = v in + > v in - bit 5 unimplemented : read as ?0? bit 4 cinv : comparator output inversion bit ? 1 = output inverted ? 0 = output not inverted bit 3 cis : comparator input switch bit ? when cm2:cm0 = 110 or 101: ? 1 = v in - connects to cin+ ? 0 = v in - connects to cin- bit 2-0 cm2:cm0 : comparator mode bits ? figure 6-2 shows the comparator modes and cm2:cm0 bit settings legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown RFPIC12F675 ds70091b-page 34 preliminary ? 2003-2013 microchip technology inc. 6.1 comparator operation a single comparator is shown in figure 6-1 , along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in -, the output of the comparator is a digital low level. when the analog input at v in + is greater than the analog input v in -, the output of the comparator is a digital high level. the shaded areas of the output of the comparator in figure 6-1 represent the uncertainty due to input offsets and response time. the polarity of the comparator output can be inverted by setting the cinv bit (cmcon<4>). clearing cinv results in a non-inverted output. a complete table showing the output state versus input conditions and the polarity bit is shown in tab le 6-1 . table 6-1: output state vs. input conditions figure 6-1: single comparator note: to use cin+ and cin- pins as analog inputs, the appropriate bits must be programmed in the cmcon (19h) register. input conditions cinv cout v in - > v in + 0 0 v in - < v in + 0 1 v in - > v in + 1 1 v in - < v in + 1 0 output v in - v in + output + ? v in + v in - note: cinv bit (cmcon<4>) is clear. ? 2003-2013 microchip technology inc. preliminary ds70091b-page 35 RFPIC12F675 6.2 comparator configuration there are eight modes of operation for the comparator. the cmcon register, shown in register 6-1 , is used to select the mode. figure 6-2 shows the eight possible modes. the trisio register controls the data direction of the comparator pins for each mode. if the comparator mode is changed, the comparator output level may not be valid for a specified period of time. refer to the specifications in section 13.0 . figure 6-2: comparator i/o operating modes note: comparator interrupts should be disabled during a comparator mode change. other - wise, a false interrupt may occur. comparator reset (por default value - low power) comparator off (lowest power) cm2:cm0 = 000 cm2:cm0 = 111 comparator without output comparator w/o output and with internal reference cm2:cm0 = 010 cm2:cm0 = 100 comparator with output and internal reference multiplexed input with internal reference and output cm2:cm0 = 011 cm2:cm0 = 101 comparator with output multiplexed input with internal reference cm2:cm0 = 001 cm2:cm0 = 110 a = analog input, ports always reads ?0? d = digital input cis = comparator input switch (cmcon<3>) gp1/cin- gp0/cin+ off (read as '0') a a gp2/cout d gp1/cin- gp0/cin+ off (read as '0') d d gp2/cout d gp1/cin- gp0/cin+ cout a a gp2/cout d gp1/cin- gp0/cin+ cout a d gp2/cout d from cv ref module gp1/cin- gp0/cin+ cout a d gp2/cout d from cv ref module gp1/cin- gp0/cin+ cout a a gp2/cout d from cv ref module cis = 0 cis = 1 gp1/cin- gp0/cin+ cout a a gp2/cout d gp1/cin- gp0/cin+ cout a a gp2/cout d from cv ref module cis = 0 cis = 1 RFPIC12F675 ds70091b-page 36 preliminary ? 2003-2013 microchip technology inc. 6.3 analog input connection considerations a simplified circuit for an analog input is shown in figure 6-3 . since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latchup may occur. a maximum source impedance of 10 k ? is recommended for the analog sources. any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current. figure 6-3: analog input mode 6.4 comparator output the comparator output, cout, is read through the cmcon register. this bit is read-only. the comparator output may also be directly output to the gp2 pin in three of the eight possible modes, as shown in figure 6-2 . when in one of these modes, the output on gp2 is asynchronous to the internal clock. figure 6-4 shows the comparator output block diagram. the trisio<2> bit functions as an output enable/ disable for the gp2 pin while the comparator is in an output mode. figure 6-4: modified comp arator output block diagram va rs < 10k a in c pin 5 pf v dd v t = 0.6v v t = 0.6v r ic leakage 500 na vss legend: c pin = input capacitance ? v t = threshold voltage ? i leakage = leakage current at the pin due to various junctions ? r ic = interconnect resistance ? r s = source impedance ? va = analog voltage note 1: when reading the gpio register, all pins configured as analog inputs will read as a ?0?. pins configured as digital inputs will convert an analog input according to the ttl input specification. 2: analog levels on any pin that is defined as a digital input, may cause the input buffer to consume more current than is specified. to gp2/t0cki pin rd cmcon set cmif bit reset to d a ta b u s cinv cv ref d en q d en q rd cmcon gp1/cin- gp0/cin+ cm2:cm0 ? 2003-2013 microchip technology inc. preliminary ds70091b-page 37 RFPIC12F675 6.5 comparator reference the comparator module also allows the selection of an internally generated voltage reference for one of the comparator inputs. the internal reference signal is used for four of the eight comparator modes. the vrcon register, register 6-2 , controls the voltage reference module shown in figure 6-5 . 6.5.1 configuring the voltage reference the voltage reference can output 32 distinct voltage levels, 16 in a high range and 16 in a low range. the following equations determine the output voltages: 6.5.2 voltage reference accuracy/error the full range of v ss to v dd cannot be realized due to the construction of the module. the transistors on the top and bottom of the resistor ladder network ( figure 6-5 ) keep cv ref from approaching v ss or v dd . the voltage reference is v dd derived and there - fore, the cv ref output changes with fluctuations in v dd . the tested absolute accuracy of the comparator voltage reference can be found in section 13.0 . figure 6-5: comparat or voltage reference block diagram 6.6 comparator response time response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output is ensured to have a valid level. if the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. otherwise, the maximum delay of the comparators should be used ( ta b l e 13-7 ). 6.7 operation during sleep both the comparator and voltage reference, if enabled before entering sleep mode, remain active during sleep. this results in higher sleep currents than shown in the power-down specifications. the additional current consumed by the comparator and the voltage reference is shown separately in the specifica - tions. to minimize power consumption while in sleep mode, turn off the comparator, cm2:cm0 = 111 , and voltage reference, vrcon<7> = 0. while the comparator is enabled during sleep, an interrupt will wake-up the device. if the device wakes up from sleep, the contents of the cmcon and vrcon registers are not affected. 6.8 effects of a reset a device reset forces the cmcon and vrcon registers to their reset states. this forces the comparator module to be in the comparator reset mode, cm2:cm0 = 000 and the voltage reference to its off state. thus, all potential inputs are analog inputs with the comparator and voltage reference disabled to consume the smallest current possible. vrr = 1 (low range): cv ref = (vr3:vr0 / 24) x v dd vrr = 0 (high range): cv ref = (v dd / 4) + (vr3:vr0 x v dd / 32) vrr 8r vr3:vr0 16-1 analog 8rrr rr cv ref to 16 stages comparator input vren v dd mux RFPIC12F675 ds70091b-page 38 preliminary ? 2003-2013 microchip technology inc. register 6-2: vrcon ? voltage refere nce control regist er (address: 99h) 6.9 comparator interrupts the comparator interrupt flag is set whenever there is a change in the output value of the comparator. software will need to maintain information about the status of the output bits, as read from cmcon<6>, to determine the actual change that has occurred. the cmif bit, pir1<3>, is the comparator interrupt flag. this bit must be reset in software by clearing it to ?0?. since it is also possible to write a '1' to this register, a simulated interrupt may be initiated. the cmie bit (pie1<3>) and the peie bit (intcon<6>) must be set to enable the interrupt. in addition, the gie bit must also be set. if any of these bits are cleared, the interrupt is not enabled, though the cmif bit will still be set if an interrupt condition occurs. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of cmcon. this will end the mismatch condition. b) clear flag bit cmif. a mismatch condition will continue to set flag bit cmif. reading cmcon will end the mismatch condition, and allow flag bit cmif to be cleared. table 6-2: registers associated with comparator module r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 vren ? vrr ? vr3 vr2 vr1 vr0 bit 7 bit 0 bit 7 vren: cv ref enable bit ? 1 = cv ref circuit powered on ? 0 = cv ref circuit powered down, no i dd drain bit 6 unimplemented: read as '0' bit 5 vrr: cv ref range selection bit ? 1 = low range ? 0 = high range bit 4 unimplemented: read as '0' bit 3-0 vr3:vr0: cv ref value selection 0 ? vr [3:0] ? 15 ? when vrr = 1: cv ref = (vr3:vr0 / 24) * v dd ? when vrr = 0: cv ref = v dd /4 + (vr3:vr0 / 32) * v dd legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: if a change in the cmcon register (cout) should occur when a read operation is being executed (start of the q2 cycle), then the cmif (pir1<3>) interrupt flag may not get set. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bod value on all other resets 0bh/8bh intcon gie peie t0ie inte gpie t0if intf gpif 0000 0000 0000 000u 0ch pir1 eeif adif ? ? cmif ? ? tmr1if 00-- 0--0 00-- 0--0 19h cmcon ? cout ? cinv cis cm2 cm1 cm0 -0-0 0000 -0-0 0000 8ch pie1 eeie adie ? ? cmie ? ? tmr1ie 00-- 0--0 00-- 0--0 85h trisio ? ? trisio5 trisio4 trisio3 trisio2 trisio1 trisio0 --11 1111 --11 1111 99h vrcon vren ? vrr ? vr3 vr2 vr1 vr0 0-0- 0000 0-0- 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ?0?. shaded cells are not used by the comparator module. ? 2003-2013 microchip technology inc. preliminary ds70091b-page 39 RFPIC12F675 7.0 analog-to-digital converter (a/d) module the analog-to-digital converter (a/d) allows conversion of an analog input signal to a 10-bit binary representa - tion of that signal. the RFPIC12F675 has four analog inputs, multiplexed into one sample and hold circuit. the output of the sample and hold is connected to the input of the converter. the converter generates a binary result via successive approximation and stores the result in a 10-bit register. the voltage reference used in the conversion is software selectable to either v dd or a voltage applied by the v ref pin. figure 7-1 shows the block diagram of the a/d. figure 7-1: a/d block diagram 7.1 a/d configuration and operation there are two registers available to control the functionality of the a/d module: 1. adcon0 ( register 7-1 ) 2. ansel ( register 7-2 ) 7.1.1 analog port pins the ans3:ans0 bits (ansel<3:0>) and the trisio bits control the operation of the a/d port pins. set the corresponding trisio bits to set the pin output driver to its high impedance state. likewise, set the corresponding ans bit to disable the digital input buffer. 7.1.2 channel selection there are four analog channels, an0 through an3. the chs1:chs0 bits (adcon0<3:2>) control which channel is connected to the sample and hold circuit. 7.1.3 voltage reference there are two options for the voltage reference to the a/d converter: either v dd is used, or an analog voltage applied to v ref is used. the vcfg bit (adcon0<6>) controls the voltage reference selection. if vcfg is set, then the voltage on the v ref pin is the reference; otherwise, v dd is the reference. 7.1.4 conversion clock the a/d conversion cycle requires 11 t ad . the source of the conversion clock is software selectable via the adcs bits (ansel<6:4>). there are seven possible clock options: ?f osc /2 ?f osc /4 ?f osc /8 ?f osc /16 ?f osc /32 ?f osc /64 ?f rc (dedicated internal rc oscillator) for correct conversion, the a/d conversion clock (1/t ad ) must be selected to ensure a minimum t ad of 1.6 ? s. ta bl e 7-1 shows a few t ad calculations for selected frequencies. gp0/an0 adc gp1/an1/v ref gp2/an2 gp4/an3 v dd v ref adon go/done vcfg = 1 vcfg = 0 chs1:chs0 adresh adresl 10 10 adfm v ss note: analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. RFPIC12F675 ds70091b-page 40 preliminary ? 2003-2013 microchip technology inc. table 7-1: t ad vs. device operating frequencies 7.1.5 starting a conversion the a/d conversion is initiated by setting the go/ done bit (adcon0<1>). when the conversion is complete, the a/d module: ? clears the go/ done bit ? sets the adif flag (pir1<6>) ? generates an interrupt (if enabled). if the conversion must be aborted, the go/ done bit can be cleared in software. the adresh:adresl registers will not be updated with the partially complete a/d conversion sample. instead, the adresh:adresl registers will retain the value of the previous conversion. after an aborted conversion, a 2 t ad delay is required before another acquisition can be initiated. following the delay, an input acquisition is automatically started on the selected channel. 7.1.6 conversion output the a/d conversion can be supplied in two formats: left or right shifted. the adfm bit (adcon0<7>) controls the output format. figure 7-2 shows the output formats. figure 7-2: 10-bit a/d result format a/d clock source (t ad ) device frequency operation adcs2:adcs0 20 mhz 5 mhz 4 mhz 1.25 mhz 2 t osc 000 100 ns (2) 400 ns (2) 500 ns (2) 1.6 ? s 4 t osc 100 200 ns (2) 800 ns (2) 1.0 ? s (2) 3.2 ? s 8 t osc 001 400 ns (2) 1.6 ? s 2.0 ? s 6.4 ? s 16 t osc 101 800 ns (2) 3.2 ? s 4.0 ? s 12.8 ? s (3) 32 t osc 010 1.6 ? s 6.4 ? s 8.0 ? s (3) 25.6 ? s (3) 64 t osc 110 3.2 ? s 12.8 ? s (3) 16.0 ? s (3) 51.2 ? s (3) a/d rc x11 2 - 6 ? s (1,4) 2 - 6 ? s (1,4) 2 - 6 ? s (1,4) 2 - 6 ? s (1,4) legend: shaded cells are outside of recommended range. note 1: the a/d rc source has a typical t ad time of 4 ? s for v dd > 3.0v. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: when the device frequency is greater than 1 mhz, the a/d rc clock source is only recommended if the conversion will be performed during sleep. note: the go/ done bit should not be set in the same instruction that turns on the a/d. adresh adresl (adfm = 0) msb lsb bit 7 bit 0 bit 7 bit 0 10-bit a/d result unimplemented: read as ?0? (adfm = 1) msb lsb bit 7 bit 0 bit 7 bit 0 unimplemented: read as ?0 10-bit a/d result ? 2003-2013 microchip technology inc. preliminary ds70091b-page 41 RFPIC12F675 register 7-1: adcon0 ? a/d cont rol register (address: 1fh) r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm vcfg ? ? chs1 chs0 go/ done adon bit 7 bit 0 bit 7 adfm: a/d result formed select bit ? 1 = right justified ? 0 = left justified bit 6 vcfg: voltage reference bit ? 1 = v ref pin ? 0 = v dd bit 5-4 unimplemented: read as zero bit 3-2 chs1:chs0: analog channel select bits ? 00 = channel 00 (an0) ? 01 = channel 01 (an1) ? 10 = channel 02 (an2) ? 11 = channel 03 (an3) bit 1 go/ done : a/d conversion status bit ? 1 = a/d conversion cycle in progress. setting this bit starts an a/d conversion cycle. ? this bit is automatically cleared by hardware when the a/d conversion has completed. ? 0 = a/d conversion completed/not in progress bit 0 adon: a/d conversion status bit 1 = a/d converter module is operating 0 = a/d converter is shut-off and consumes no operating current legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown RFPIC12F675 ds70091b-page 42 preliminary ? 2003-2013 microchip technology inc. register 7-2: ansel ? analog select register (address: 9fh) u-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 r/w-1 ? adcs2 adcs1 adcs0 ans3 ans2 ans1 ans0 bit 7 bit 0 bit 7 unimplemented: read as ?0?. bit 6-4 adcs<2:0>: a/d conversion clock select bits 000 = f osc /2 001 = f osc /8 010 = f osc /32 x11 = f rc (clock derived from a dedicated internal oscillator = 500 khz max) 100 = f osc /4 101 = f osc /16 110 = f osc /64 bit 3-0 ans3:ans0: analog select bits ? (between analog or digital function on pins an<3:0>, respectively.) 1 = analog input; pin is assigned as analog input (1) 0 = digital i/o; pin is assigned to port or special function note 1: setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change. the corresponding trisio bit must be set to input mode in order to allow external control of the voltage on the pin. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2003-2013 microchip technology inc. preliminary ds70091b-page 43 RFPIC12F675 7.2 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 7-3 . the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), see figure 7-3 . the maximum recommended imped - ance for analog sources is 10 k ? . as the impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 7-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. to calculate the minimum acquisition time, t acq , see the pic mid-range reference manual (ds33023). equation 7-1: acquisition time figure 7-3: analog input model t acq t c t acq = = = = = = = = amplifier settling time + hold capacitor charging time + temperature coefficient t amp + t c + t coff 2 ? s + t c + [(temperature -25 c)(0.05 ? s/c)] c hold (r ic + r ss + r s ) in(1/2047) - 120pf (1k ? + 7k ? + 10k ? ) in(0.0004885) 16.47 ? s 2 ? s + 16.47 ? s + [(50c -25 ? c)(0.05 ? s/ ? c) 19.72 ? s note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 10 k ? . this is required to meet the pin ? leakage specification. c pin va r s anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic ? 1k sampling switch ss r ss c hold = dac capacitance v ss 6v sampling switch 5v 4v 3v 2v 567891011 (k ? ) v dd = 120 pf 500 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions RFPIC12F675 ds70091b-page 44 preliminary ? 2003-2013 microchip technology inc. 7.3 a/d operation during sleep the a/d converter module can operate during sleep. this requires the a/d clock source to be set to the internal rc oscillator. when the rc clock source is selected, the a/d waits one instruction before starting the conversion. this allows the sleep instruction to be executed, thus eliminating much of the switching noise from the conversion. when the conversion is complete, the go/ done bit is cleared, and the result is loaded into the adresh:adresl registers. if the a/d interrupt is enabled, the device awakens from sleep. if the a/d interrupt is not enabled, the a/d module is turned off, although the adon bit remains set. when the a/d clock source is something other than rc, a sleep instruction causes the present conversion to be aborted, and the a/d module is turned off. the adon bit remains set. 7.4 effects of reset a device reset forces all registers to their reset state. thus the a/d module is turned off and any pending conversion is aborted. the adresh:adresl registers are unchanged. table 7-2: summary of a/d registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bod value on all other resets 05h gpio ? ? gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 --xx xxxx --uu uuuu 0bh, 8bh intcon gie peie t0ie inte gpie t0if intf gpif 0000 0000 0000 000u 0ch pir1 eeif adif ? ? cmif ? ? tmr1if 00-- 0--0 00-- 0--0 1eh adresh most significant 8 bits of the left shifted a/d result or 2 bits of the right shifted result xxxx xxxx uuuu uuuu 1fh adcon0 adfm vcfg ? ? chs1 chs0 go adon 00-- 0000 00-- 0000 85h trisio ? ? trisio5 trisio4 trisio3 trisio2 trisio1 trisio0 --11 1111 --11 1111 8ch pie1 eeie adie ? ? cmie ? ? tmr1ie 00-- 0--0 00-- 0--0 9eh adresl least significant 2 bits of the left shifted a/d result or 8 bits of the right shifted result xxxx xxxx uuuu uuuu 9fh ansel ? adcs2 adcs1 adcs0 ans3 ans2 ans1 ans0 -000 1111 -000 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used for a/d converter module. ? 2003-2013 microchip technology inc. preliminary ds70091b-page 45 RFPIC12F675 8.0 data eeprom memory the eeprom data memory is readable and writable during normal operation (full v dd range). this memory is not directly mapped in the register file space. instead, it is indirectly addressed through the special function registers. there are four sfrs used to read and write this memory: ? eecon1 ? eecon2 (not a physically implemented register) ? eedata ? eeadr eedata holds the 8-bit data for read/write, and eeadr holds the address of the eeprom location being accessed. the RFPIC12F675 devices have 128 bytes of data eeprom with an address range from 0h to 7fh. the eeprom data memory allows byte read and write. a byte write automatically erases the location and writes the new data (erase before write). the eeprom data memory is rated for high erase/write cycles. the write time is controlled by an on-chip timer. the write time will vary with voltage and temperature as well as from chip to chip. please refer to ac specifications for exact limits. when the data memory is code protected, the cpu may continue to read and write the data eeprom memory. the device programmer can no longer access this memory. additional information on the data eeprom is available in the pic mid-range reference manual (ds33023). register 8-1: eedat ? eeprom data register (address: 9ah) register 8-2: eeadr ? eeprom address register (address: 9bh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eedat7 eedat6 eedat5 eedat4 eedat3 eedat2 eedat1 eedat0 bit 7 bit 0 bit 7-0 eedatn : byte value to write to or read from data eeprom legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? eadr6 eadr5 eadr4 eadr3 eadr2 eadr1 eadr0 bit 7 bit 0 bit 7 unimplemented : should be set to '0' bit 6-0 eeadr : specifies one of 128 locations for eeprom read/write operation legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown RFPIC12F675 ds70091b-page 46 preliminary ? 2003-2013 microchip technology inc. 8.1 eeadr the eeadr register can address up to a maximum of 128 bytes of data eeprom. only seven of the eight bits in the register (eeadr<6:0>) are required. the msb (bit 7) is ignored. the upper bit should always be ?0? to remain upward compatible with devices that have more data eeprom memory. 8.2 eecon1 and eecon2 registers eecon1 is the control register with four low order bits physically implemented. the upper four bits are non- implemented and read as '0's. control bits rd and wr initiate read and write, respectively. these bits cannot be cleared, only set, in software. they are cleared in hardware at completion of the read or write operation. the inability to clear the wr bit in software prevents the accidental, premature termination of a write operation. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a mclr reset, or a wdt time-out reset during normal opera - tion. in these situations, following reset, the user can check the wrerr bit, clear it, and rewrite the location. the data and address will be cleared, therefore, the eedata and eeadr registers will need to be re- initialized. interrupt flag bit eeif in the pir1 register is set when write is complete. this bit must be cleared in software. eecon2 is not a physical register. reading eecon2 will read all '0's. the eecon2 register is used exclusively in the data eeprom write sequence. register 8-3: eecon1 ? eeprom control register (address: 9ch) u-0 u-0 u-0 u-0 r/w-x r/w-0 r/s-0 r/s-0 ? ? ? ? wrerr wren wr rd bit 7 bit 0 bit 7-4 unimplemented: read as ?0? bit 3 wrerr: eeprom error flag bit 1 = a write operation is prematurely terminated (any mclr reset, any wdt reset during ? normal operation or bod detect) 0 = the write operation completed bit 2 wren: eeprom write enable bit 1 = allows write cycles 0 = inhibits write to the data eeprom bit 1 wr : write control bit 1 = initiates a write cycle (the bit is cleared by hardware once write is complete. the wr bit can only be set, not cleared, in software.) 0 = write cycle to the data eeprom is complete bit 0 rd : read control bit 1 = initiates an eeprom read (read takes one cycle. rd is cleared in hardware. the rd bit can only be set, not cleared, in software.) 0 = does not initiate an eeprom read legend: s = bit can only be set ? r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ? 2003-2013 microchip technology inc. preliminary ds70091b-page 47 RFPIC12F675 8.3 reading the eeprom data memory to read a data memory location, the user must write the address to the eeadr register and then set control bit rd (eecon1<0>), as shown in example 8-1 . the data is available, in the very next cycle, in the eedata register. therefore, it can be read in the next instruction. eedata holds this value until another read, or until it is written to by the user (during a write operation). example 8-1: data eeprom read 8.4 writing to the eeprom data memory to write an eeprom data location, the user must first write the address to the eeadr register and the data to the eedata register. then the user must follow a specific sequence to initiate the write for each byte, as shown in example 8-2 . example 8-2: data eeprom write the write will not initiate if the above sequence is not exactly followed (write 55h to eecon2, write aah to eecon2, then set wr bit) for each byte. we strongly recommend that interrupts be disabled during this code segment. a cycle count is executed during the required sequence. any number that is not equal to the required cycles to execute the required sequence will prevent the data from being written into the eeprom. additionally, the wren bit in eecon1 must be set to enable write. this mechanism prevents accidental writes to data eeprom due to errant (unexpected) code execution (i.e., lost programs). the user should keep the wren bit clear at all times, except when updating eeprom. the wren bit is not cleared by hardware. after a write sequence has been initiated, clearing the wren bit will not affect this write cycle. the wr bit will be inhibited from being set unless the wren bit is set. at the completion of the write cycle, the wr bit is cleared in hardware and the ee write complete interrupt flag bit (eeif) is set. the user can either enable this interrupt or poll this bit. the eeif bit (pir<7>) register must be cleared by software. 8.5 write verify depending on the application, good programming practice may dictate that the value written to the data eeprom should be verified (see example 8-3 ) to the desired value to be written. example 8-3: write verify 8.5.1 using the data eeprom the data eeprom is a high-endurance, byte address - able array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). frequently changing values will typically be updated more often than specifications d120 or d120a. if this is not the case, an array refresh must be performed. for this reason, variables that change infrequently (such as constants, ids, calibration, etc.) should be stored in flash program memory. 8.6 protection against spurious write there are conditions when the device may not want to write to the data eeprom memory. to protect against spurious eeprom writes, various mechanisms have been built in. on power-up, wren is cleared. also, the power-up timer (72 ms duration) prevents eeprom write. the write initiate sequence and the wren bit together help prevent an accidental write during: ?brown-out ? power glitch ? software malfunction bsf status,rp0 ;bank 1 movlw config_addr ; movwf eeadr ;address to read bsf eecon1,rd ;ee read movf eedata,w ;move data to w bsf status,rp0 ;bank 1 bsf eecon1,wren ;enable write bcf intcon,gie ;disable ints movlw 55h ;unlock write movwf eecon2 ; movlw aah ; movwf eecon2 ; bsf eecon1,wr ;start the write bsf intcon,gie ;enable ints required sequence bcf status,rp0 ;bank 0 : ;any code bsf status,rp0 ;bank 1 read movf eedata,w ;eedata not changed ;from previous write bsf eecon1,rd ;yes, read the ;value written xorwf eedata,w btfss status,z ;is data the same goto write_err ;no, handle error : ;yes, continue RFPIC12F675 ds70091b-page 48 preliminary ? 2003-2013 microchip technology inc. 8.7 data eeprom operation during code protect data memory can be code protected by programming the cpd bit to ?0?. when the data memory is code protected, the cpu is able to read and write data to the data eeprom. it is recommended to code protect the program memory when code protecting data memory. this prevents anyone from programming zeroes over the existing code (which will execute as nop s) to reach an added routine, programmed in unused program memory, which outputs the contents of data memory. programming unused locations to ?0? will also help prevent data memory code protection from becoming breached. table 8-1: registers/bits associated with data eeprom address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bod value on all other resets 0ch pir1 eeif adif ? ? cmif ? ? tmr1if 00-- 0--0 00-- 0--0 9ah eedata eeprom data register 0000 0000 0000 0000 9bh eeadr ? eeprom address register -000 0000 -000 0000 9ch eecon1 ? ? ? ? wrerr wren wr rd ---- x000 ---- q000 9dh eecon2 (1) eeprom control register 2 ---- ---- ---- ---- legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. ? shaded cells are not used by data eeprom module. note 1: eecon2 is not a physical register. ? 2003-2013 microchip technology inc. preliminary ds70091b-page 49 RFPIC12F675 9.0 uhf ask/fsk transmitter 9.1 transmitter operation the transmitter is a fully integrated uhf ask/fsk transmitter consisting of crystal oscillator, phase- locked loop (pll), power amplifier (pa) with open- collector output, and mode control logic. there are 3 variations of this device to optimize its performance for the most commonly used frequency bands. table 9-1: frequency bands the internal structure of the transmitter is shown in figure 9-1 . a colpitts oscillator generates the reference frequency set by the attached crystal. the voltage controlled oscillator (vco) converts the voltage on the lf pin to a frequency. this frequency is divided by 32 and compared to the crystal reference. if the frequency or phase does not match the reference, the charge pump corrects the voltage on the lf pin. the vco output signal is also amplified by the pa, whose single ended output drives the user?s antenna. the external components required are a crystal to set the transmit frequency, a supply bypass capacitor, and two to seven biasing/impedance matching components to get maximum power to the antenna. the two control signals from the microcontroller are connected exter - nally for maximum design flexibility. the RFPIC12F675 is capable of transmitting data by amplitude shift keying (ask) or frequency shift keying (fsk). the RFPIC12F675 is a radio frequency (rf) emitting device. wireless rf devices are governed by a country?s regulating agency. for example, in the united states it is the federal communications committee (fcc) and in europe it is the european conference of postal and telecommunications administrations (cept). it is the responsibility of the designer to ensure that their end product conforms to rules and regulations of the country of use and/or sale. figure 9-1: transmitter block diagram 9.2 supply voltage (v ddrf , v ssrf ) pins v ddrf and v ssrf supply power and ground respectively to the transmitter. these power pins are separate from power supply pins v dd and v ss to the microcontroller . both v ssrf pins should be tied to the ground plane with the shortest possible traces. the microcontroller ground should be tied to the same rf ground potential. however, the v ddrf supply can be at a different potential than the microcontroller as long as the rfen and data input levels are within specifica - tion limits. device frequency modulation RFPIC12F675k 290-350 mhz ask/fsk RFPIC12F675f 390-450 mhz ask/fsk RFPIC12F675h 850-930 mhz ask/fsk rf devices require correct board level implementa - tion in order to meet regulatory requirements. layout considerations are listed at the end of each subsec - tion. it is required to place a ground plane on the pcb to reduce unwanted radio frequency emissions. layout considerations - provide low impedance power and ground traces to minimize spurious emissions. a two-sided pcb with a ground plane on the bottom layer is highly recommended. separate bypass capacitors should be connected as close as possible to each of the supply pins v dd and v ddrf . connect both v ssrf pins to the ground plane using multiple pcb vias adjacent to the v ssrf pads. do not share these pcb vias with other ground traces. filter the v ddrf with an rc filter if the microcontroller noise spurs exceed regulatory limits. clock divider voltage controlled oscillator rf power amplifier crystal oscillator phase/freq detector charge pump fsk switch refclk rf control logic fsk out v ddrf v ssrf v ssrf rfen ant lf rfxtal ps data ask divide by 32 data fsk RFPIC12F675 ds70091b-page 50 preliminary ? 2003-2013 microchip technology inc. 9.3 crystal oscillator the transmitter crystal oscillator is a colpitts oscillator that provides the reference frequency to the pll. it is independent of the microcontroller oscillator. an external crystal or ac coupled reference signal is connected to the xtal pin. the transmit frequency is fixed and determined by the crystal frequency according to the formula: due to the flexible selection of transmit frequency, the resulting crystal frequency may not be a standard off- the-shelf value. therefore, for some carrier frequencies the designer will have to consult a crystal manufacturer and have a custom crystal manufactured. for background information on crystal selection see application note an588, pic ? microcontroller oscilla - tor design guide , and an826 crystal oscillator basics and crystal selection for rfpic? and pic ? devices . for ask modulation the crystal can be connected directly from rfxtal to ground, or in series with an additional capacitor to trim the frequency. figure 9-2 shows how the crystal is connected and table 9-2 shows how the frequency of a typical crystal changes with capacitance. the oscillator is enabled when the rfen input is high. it takes the crystal approximately 1 ms to start oscillat - ing. higher frequency crystals start-up faster than lower frequencies. the crystal oscillator start time (t on ) is listed in ta b l e 13-11 , transmitter ac characteristics. this start-up time is mainly due to the crystal building up an oscillation, but also includes the time for the pll to lock on the crystal frequency. 9.4 ask modulation in ask modulation the data is transmitted by varying the output power. the data ask pin enables the pa, toggling the pin turns the rf output signal on and off. a simple receiver using a tuned filter and peak detector diode can capture the data. a more advanced super - heterodyne receiver such as the rfrxd0420 can greatly increase the range and reduce susceptibility to interference. in ask mode the data fsk and fsk out pins are not used and should both be tied to ground. an example of a typical ask circuit is shown in figure 9-5 . the c1 capacitor can be replaced by a short to simplify the transmitter if the receiver has a wide enough bandwidth. for a very narrowband receiver the c1 capacitor may need to be replaced by a trimmer cap to tune the transmitter to the exact frequency. figure 9-2: ask crystal circuit table 9-2: xtal osc approximate freq. vs. capacitance (ask mode) (1) 32 ? ? rfxtal transmit f f xtal RFPIC12F675k/f/h x1 c1 c1 predicted frequency (mhz) ppm from 13.55 mhz transmit frequency (mhz) (32 * f xtal ) 22 pf 13.551438 +106 433.646 39 pf 13.550563 +42 433.618 100 pf 13.549844 -12 433.595 150 pf 13.549672 -24 433.5895 470 pf 13.549548 -33 433.5856 1000 pf 13.549344 -48 433.579 note 1: standard operating conditions (unless otherwise stated) t a = 25c, rfen = 1, v ddrf = 3v, ? f xtal = 13.55 mhz ? 2003-2013 microchip technology inc. preliminary ds70091b-page 51 RFPIC12F675 9.5 fsk modulation in fsk modulation the transmit data is sent by varying the output frequency. this is done by loading the reference crystal with extra capacitance to pull it to a slightly lower frequency which the pll then tracks. switching the capacitance in and out with the data signal toggles the transmitter between two frequencies. these two crystal based frequencies are then multiplied by 32 for the rf transmit frequency. unlike the ask transmit frequency the fsk center frequency is not actually transmitted. it is the artificial point half way between the two transmitted frequencies, calculated with this formula. the other important parameter in fsk is the frequency deviation of the transmit frequency. this measures how far the frequency will swing from the center frequency. single ended deviation is calculated with this formula. an fsk receiver will specify its optimal value of deviation. the single ended deviation must be greater than data rate / 4. the minimum deviation is usually limited by the frequency accuracy of the transmitter and receiver components. the maximum deviation is usually limited by the pulling characteristics of the transmitter crystal. an extra capacitor and the internal switch are added to the ask design to build an fsk transmitter as shown in figure 9-3 . the c1 capacitor in series with the crystal determines the maximum frequency. with the data fsk pin high the fsk out pin is open and the c2 capacitor does not affect the frequency. when the data fsk pin goes low, fsk out shorts to ground, and the c2 is thrown in parallel with c1. the sum of the two caps pulls the oscillation frequency lower as shown in figure 9-4 . in fsk mode the data ask pin should be tied high to enable the pa. the fsk circuit is shown in figure 9-6 . use accurate crystals for narrow bandwidth systems and large values for c1 to reduce frequency drift. figure 9-3: fsk crystal circuit figure 9-4: frequency pulling table 9-3: typical transmit center frequency and deviation (fsk mode) (1) 2 min max f f f c ? ? 2 min max f f f ? ? ? xtal RFPIC12F675k/f/h x1 c1 c2 fskout frequency (mhz) fmax fmin c1 c1||c2 data fsk = 1 data fsk = 0 load capacitance (pf) c2 = 1000 pf c2 = 100 pf c2 = 47 pf c1 (pf) freq (mhz) / dev (khz) freq (mhz) / dev (khz) freq (mhz) / dev (khz) 22 433.612 / 34 433.619 / 27 433.625 / 21 33 433.604 / 25 433.610 / 19 433.614 / 14 39 433.598 / 20 433.604 / 14 433.608 / 10 47 433.596 / 17 433.601 / 11.5 433.604 / 8 68 433.593 / 13 433.598 / 9 433.600 / 5.5 100 433.587 / 8 ? ? note 1: standard operating conditions, t a = 25c, rf en = 1, v ddrf = 3v, f xtal = 13.55 mhz RFPIC12F675 ds70091b-page 52 preliminary ? 2003-2013 microchip technology inc. figure 9-5: typical as k transmitter schematic figure 9-6: typical fsk transmitter schematic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 clkout rfenin v ddrf ant v ssrf v ssrf u1 ps v ss gp0/an0/cin+/icspdat gp1/an1/cin-/v ref /icspclk gp2/an2/t0cki/int/cout gp3/mclr/v pp gp4/an3/t1g/osc2/clkout gp5/t1cki/osc1/clkin v dd lf data ask rfxtal data fsk fsk out RFPIC12F675k +v +v +v + - bt1 3v c1 c3 0.1 f c4 100 pf c5 100 pf c6 5 pf c7 4 pf 120 nh l1 r1 r2 4.7 k sw1 sw2 19 20 x1 cr2032 lithium cell loop antenna c1 can be shorted r1 can be omitted 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 clkout rfenin v ddrf ant v ssrf v ssrf u1 ps v ss gp0/an0/cin+/icspdat gp1/an1/cin-/v ref /icspclk gp2/an2/t0cki/int/cout gp3/mclr/v pp gp4/an3/t1g/osc2/clkout gp5/t1cki/osc1/clkin v dd lf data ask rfxtal data fsk fsk out RFPIC12F675k +v +v +v +v + - bt1 3v c1 c2 1000 pf c3 0.1 f c4 100 pf c5 100 pf c6 5 pf c7 4 pf 120 nh l1 r1 220 k r2 4.7 k sw1 sw2 19 20 x1 cr2032 lithium cell loop antenna 13.55 mhz 39 pf ? 2003-2013 microchip technology inc. preliminary ds70091b-page 53 RFPIC12F675 9.6 clock output the clock output is available to the microcontroller or other circuits requiring an accurate reference frequency. this signal would typically be used to correct the internal rc oscillator for system designs that require accurate bit synchronization or tight time division multiplexing. the refclk output can connect directly to the t0cki or t1cki. the refclk output frequency is the crystal oscillator divided by 4 on the RFPIC12F675k and RFPIC12F675f. for the RFPIC12F675h the crystal oscillator is divided by 8. 9.7 phase-locked loop filter the lf pin connects to an internal node on the pll filter. typically the pin should not be connected. in specialized cases it may be necessary to load this pin with extra capacitance to ground. adding capacitance reduces the loop filter bandwidth which trades off an increase in phase noise for a reduction in clock spurs. useful diagnostic measurements can be taken on the lf pin with a high impedance, low capacitance probe. measuring the time from rfen going high until the lf voltage stabilizes will determine the minimum delay before the start of a transmission. for more information on pll filters refer to application note an846 basic pll filters for the rfpic?/rfhcs . 9.8 power amplifier the pll output feeds the power amplifier (pa) which drives the open-collector ant output. the output should be dc biased with an inductor to the v ddrf supply. the output impedance must be matched to the load impedance to deliver the maximum power. this is typically done with a transformer or tapped capacitor circuit. failure to match the impedance may cause excessive spurious and harmonic emissions. for more information on transformer matching see application note an831, matching small loop antennas to rfpic? devices . for more information on tapped capacitor matching see application note an242 designing an fcc approved ask rfpic? transmitter . the transmit output power can be adjusted in five discrete steps from +9 dbm to -70 dbm by varying the voltage on the ps pin. since the ps pin has an internal 8 ? a source the voltage can be set with a resistor from the ps pin to ground as shown in figure 9-7 . some possible resistor values to set the current are shown in table 9-4 . it is usually desirable to select the lowest power level step that does not compromise communications reli - ablity. the most important benefit is the conservation of battery power. another reason is to make it easier to pass regulatory limits. and a third reason is to reduce interference to other communications in the shared rf spectrum. small inefficient antennas will require higher power level settings than larger efficient antennas. figure 9-7: .power select circuit table 9-4: power select resistor selection (1,2) layout considerations - keep the clock trace short and narrow yet as far as possible from other traces to reduce capacitance and the associated current draw. if the refclk trace must pass near the crystal and lf nodes then shield them with ground traces. layout considerations - keep traces short and if the optional loop filter capacitor is required, place it as close as possible to the lf pin with its own via to the ground plane. ps RFPIC12F675 r1 v ps i ps = 8 ? a to powe r select circuitry power step output power (dbm) ps voltage (volts) r1 resistance ( ? ) rf transmitter current (ma) 4 9 1.6 open 10.7 3 2 0.8 100k (3) 6.5 2 -4 0.4 47k (3) 4.7 1 -12 0.2 22k (3) 3.5 0 -70 0.1 short 2.7 note 1: standard operating conditions, t a = 25c, rfen = 1, v ddrf = 3v, f transmit = 433.92 mhz 2: typical values, for complete specifications see data sheet section 13.0 . 3: r1 resistor variations plus i ps current supply variations must not exceed v ps step limits. RFPIC12F675 ds70091b-page 54 preliminary ? 2003-2013 microchip technology inc. 9.9 digital control signals the mode control logic pin rfen controls the operation of the transmitter. when rfen goes high, the crystal oscillator starts up. the voltage on the lf pin ramps up proportionally to the rf frequency. the pll can lock onto the frequency faster than the start - ing up crystal can stabilize. when the lf pin reaches 0.8v, the rf frequency is close to locked on the crys - tal frequency. this initiates a 150 microsecond delay to ensure that the pll settles. after the delay, the ps bias current and power amplifier are enabled to start transmitting when data ask goes high. when rfen is low, the transmitter goes into a very low power standby mode. the power amplifier is disabled and the crystal oscillator stops. the rfen pin has an internal pull-down resistor. 9.10 low voltage output disable the RFPIC12F675 transmitter has a built in low voltage disable centered at about 1.85v. if the supply voltage drops below this voltage the power amplifier is disabled to prevent uncontrolled transmissions. ? 2003-2013 microchip technology inc. preliminary ds70091b-page 55 RFPIC12F675 10.0 special features of the cpu certain special circuits that deal with the needs of real time applications are what sets a microcontroller apart from other processors. the RFPIC12F675 family has a host of such features intended to: ? maximize system reliability ? minimize cost through elimination of external components ? provide power saving operating modes and offer code protection. these features are: ? oscillator selection ? reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out detect (bod) ? interrupts ? watchdog timer (wdt) ? sleep ? code protection ? id locations ? in-circuit serial programming the RFPIC12F675 has a watchdog timer that is controlled by configuration bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. there is also circuitry to reset the device if a brown-out occurs, which can provide at least a 72 ms reset. with these three functions on-chip, most applications need no external reset circuitry. the sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through: ? external reset ? watchdog timer wake-up ? an interrupt several oscillator options are also made available to allow the part to fit the application. the intosc option saves system cost while the lp crystal option saves power. a set of configuration bits are used to select various options (see register 10-1 ). RFPIC12F675 ds70091b-page 56 preliminary ? 2003-2013 microchip technology inc. 10.1 configuration bits the configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1') to select various device configurations, as shown in register 10-1 . these bits are mapped in program memory location 2007h. register 10-1: config ? configuration word (address: 2007h) note: address 2007h is beyond the user program memory space. it belongs to the special configuration memory space (2000h - 3fffh), which can be accessed only during programming. see RFPIC12F675 program - ming specification for more information. r/p-1 r/p-1 u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 bg1 bg0 ? ? ? cpd cp boden mclre pwrte wdte f0sc2 f0sc1 f0sc0 bit 13 bit 0 bit 13-12 bg1:bg0: bandgap calibration bits for bod and por voltage (1) 00 = lowest bandgap voltage 11 = highest bandgap voltage bit 11-9 unimplemented : read as ?0? bit 8 cpd : data code protection bit (2) ? 1 = data memory code protection is disabled ? 0 = data memory code protection is enabled bit 7 cp : code protection bit (3) ? 1 = program memory code protection is disabled ? 0 = program memory code protection is enabled bit 6 boden : brown-out detect enable bit (4) ? 1 = bod enabled ? 0 = bod disabled bit 5 mclre : gp3/ mclr pin function select (5) ? 1 = gp3/ mclr pin function is mclr ? 0 = gp3/ mclr pin function is digital i/o, mclr internally tied to v dd bit 4 pwrte : power-up timer enable bit ? 1 = pwrt disabled ? 0 = pwrt enabled bit 3 wdte : watchdog timer enable bit ? 1 = wdt enabled ? 0 = wdt disabled bit 2-0 fosc2:fosc0 : oscillator selection bits 111 = rc oscillator: clkout function on gp4/osc2/clkout pin, rc on gp5/osc1/clkin ? 110 = rc oscillator: i/o function on gp4/osc2/clkout pin, rc on gp5/osc1/clkin ? 101 = intosc oscillator: clkout function on gp4/ osc2/clkout pin, i/o function on gp5/osc1/clkin ? 100 = intosc oscillator: i/o function on gp4/osc2/clkout pin, i/o function on gp5/osc1/clkin ? 011 = ec: i/o function on gp4/osc2/clkout pin, clkin on gp5/osc1/clkin ? 010 = hs oscillator: high speed crystal/resonator on gp4/osc2/clkout and gp5/osc1/clkin ? 001 = xt oscillator: crystal/resonator on gp4/osc2/clkout and gp5/osc1/clkin ? 000 = lp oscillator: low power crystal on gp4/osc2/clkout and gp5/osc1/clkin note 1: the bandgap calibration bits are factory progra mmed and must be read and saved prior to erasing the device as specified in the RFPIC12F675 programming specification. these bits are reflected in an export of the configuration word. microchip development tools maintain all calibration bits to factory settings. 2: the entire data eeprom will be erased when the code protection is turned off. 3: the entire program memory will be erased, including osccal value, when the code protection is turned off. 4: enabling brown-out detect does not automatically enable power-up timer. 5: when mclr is asserted in intosc or rc mode, the internal clock oscillator is disabled. legend: p = programmed using icsp r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown ? 2003-2013 microchip technology inc. preliminary ds70091b-page 57 RFPIC12F675 10.2 oscillator configurations 10.2.1 oscillator types the RFPIC12F675 can be operated in eight different oscillator option modes. the user can program three configuration bits (fosc2 through fosc0) to select one of these eight modes: ? lp low power crystal ? xt crystal/resonator ? hs high speed crystal/resonator ? rc external resistor/capacitor (2 modes) ? intosc internal oscillator (2 modes) ? ec external clock in 10.2.2 crystal oscillator / ceramic resonators in xt, lp or hs modes a crystal or ceramic resonator is connected to the osc1 and osc2 pins to establish oscillation (see figure 10-1 ). the RFPIC12F675 oscillator design requires the use of a parallel cut crystal. use of a series cut crystal may yield a frequency outside of the crystal manufacturers specifications. when in xt, lp or hs modes, the device can have an external clock source to drive the osc1 pin (see figure 10-2 ). figure 10-1: crystal operation (or ceramic resonator) hs, xt or lp osc configuration figure 10-2: external clock input operation (hs, xt, ec, or lp osc configuration) table 10-1: capacitor selection for ceramic resonators table 10-2: capacitor selection for crystal oscillator note: additional information on oscillator config - urations is available in the picmicro tm mid-range reference manual , (ds33023) note 1: see table 10-1 and table 10-2 for recommended values of c1 and c2. 2: a series resistor may be required for at strip cut crystals. 3: rf varies with the oscillator mode selected (approx. value = 10 m ??? c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to internal pic12f629/675 logic rs (2) ranges characterized: mode freq osc1(c1) osc2(c2) xt 455 khz 2.0 mhz 4.0 mhz 68 - 100 pf 15 - 68 pf 15 - 68 pf 68 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf note 1: higher capacitance increases the stability of the oscillator but also increases the start-up time. these values are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. mode freq osc1(c1) osc2(c2) lp 32 khz 68 - 100 pf 68 - 100 pf xt 100 khz 2 mhz 4 mhz 68 - 150 pf 15 - 30 pf 15 - 30 pf 150 - 200 pf 15 - 30 pf 15 - 30 pf hs 8 mhz 10 mhz 20 mhz 15 - 30 pf 15 - 30 pf 15 - 30 pf 15 - 30 pf 15 - 30 pf 15 - 30 pf note 1: higher capacitance increases the stability of the oscillator but also increases the start-up time. these values are for design guidance only. rs may be required in hs mode as well as xt mode to avoid overdriving crystals with low drive level specification. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. clock from external system pic12f629/675 osc1 osc2 (1) open note 1: functions as gp4 in ec osc mode. RFPIC12F675 ds70091b-page 58 preliminary ? 2003-2013 microchip technology inc. 10.2.3 external clock in for applications where a clock is already available elsewhere, users may directly drive the RFPIC12F675 provided that this external clock source meets the ac/ dc timing requirements listed in section 13.0 . figure 10-2 shows how an external clock circuit should be configured. 10.2.4 rc oscillator for applications where precise timing is not a require - ment, the rc oscillator option is available. the operation and functionality of the rc oscillator is dependent upon a number of variables. the rc oscillator frequency is a function of: ? supply voltage ? resistor (r ext ) and capacitor (c ext ) values ? operating temperature the oscillator frequency will vary from unit to unit due to normal process parameter variation. the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to account for the tolerance of the external r and c components. figure 10-3 shows how the r/c combination is connected. two options are available for this oscillator mode which allow gp4 to be used as a general purpose i/o or to output f osc /4. figure 10-3: rc oscillator mode 10.2.5 internal 4 mh z oscillator when calibrated, the internal oscillator provides a fixed 4 mhz (nominal) system clock. see electrical specifications, section 13.0 , for information on variation over voltage and temperature. two options are available for this oscillator mode which allow gp4 to be used as a general purpose i/o or to output f osc /4. 10.2.5.1 calibrating the internal oscillator a calibration instruction is programmed into the last location of program memory. this instruction is a retlw xx , where the literal is the calibration value. the literal is placed in the osccal register to set the calibration of the internal oscillator. example 10-1 demonstrates how to calibrate the internal oscillator. for best operation, decouple (with capacitance) v dd and v ss as close to the device as possible. example 10-1: calibrating the internal oscillator 10.2.6 clkout the RFPIC12F675 devices can be configured to provide a clock out signal in the intosc and rc oscillator modes. when configured, the oscillator frequency divided by four (f osc /4) is output on the gp4/osc2/ clkout pin. f osc /4 can be used for test purposes or to synchronize other logic. note: the microcontroller oscillator is indepen - dent of the rf peripheral oscillator. an accurate time-base is still possible with only one crystal. use the rf crystal on transmitter and tie the refclk signal back into t0cki or t1cki to correct the rc, intosc, or ec clocks. since ref - clk is only active when rfen=1, it is not a suitable source for clkin. gp4/osc2/clkout c ext v dd r ext v ss pic12f629/675 gp5/osc1/ f osc /4 internal clock clkin note: erasing the device will also erase the pre- programmed internal calibration value for the internal oscillator. the calibration value must be saved prior to erasing part as specified in the RFPIC12F675 programming specification. microchip development tools maintain all calibration bits to factory settings. bsf status, rp0 ;bank 1 call 3ffh ;get the cal value movwf osccal ;calibrate bcf status, rp0 ;bank 0 ? 2003-2013 microchip technology inc. preliminary ds70091b-page 59 RFPIC12F675 10.3 reset the RFPIC12F675 differentiates between various kinds of reset: a) power-on reset (por) b) wdt reset during normal operation c) wdt reset during sleep d) mclr reset during normal operation e) mclr reset during sleep f) brown-out detect (bod) some registers are not affected in any reset condition; their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?reset state? on: ? power-on reset ? mclr reset ?wdt reset ? wdt reset during sleep ? brown-out detect (bod) reset they are not affected by a wdt wake-up, since this is viewed as the resumption of normal operation. to and pd bits are set or cleared differently in different reset situations as indicated in table 10-4 . these bits are used in software to determine the nature of the reset. see ta b l e 10-7 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 10-4 . the mclr reset path has a noise filter to detect and ignore small pulses. see ta b l e 13-4 in electrical specifications section for pulse width specification. figure 10-4: simplified block di agram of on-chip reset circuit s r q external reset mclr / v dd osc1/ wdt module v dd rise detect ost/pwrt on-chip (1) rc osc wdt time-out power-on reset ost pwrt chip_reset 10-bit ripple counter reset enable ost enable pwrt sleep see table 10-3 for time-out situations. note 1: this is a separate oscillator from the intosc/ec oscillator. brown-out detect boden clkin pin v pp pin 10-bit ripple counter q RFPIC12F675 ds70091b-page 60 preliminary ? 2003-2013 microchip technology inc. 10.3.1 mclr the RFPIC12F675 devices have a noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. the behavior of the esd protection on the mclr pin has been altered from previous devices of this family. voltages applied to the pin that exceed its specification can result in both mclr resets and excessive current beyond the device specification during the esd event. for this reason, microchip recommends that the mclr pin no longer be tied directly to v dd . the use of an rc network, as shown in figure 10-5 , is suggested. an internal mclr option is enabled by setting the mclre bit in the configuration word. when enabled, mclr is internally tied to v dd . no internal pull-up option is available for the mclr pin. figure 10-5: recommended mclr circuit 10.3.2 power-on reset (por) the on-chip por circuit holds the chip in reset until v dd has reached a high enough level for proper operation. to take advantage of the por, simply tie the mclr pin through a resistor to v dd . this will eliminate external rc components usually needed to create power-on reset. a maximum rise time for v dd is required. see electrical specifications for details (see section 13.0 ). when the device starts normal operation (exits the reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. for additional information, refer to application note an607 ?power-up trouble shooting? . 10.3.3 power-up timer (pwrt) the power-up timer provides a fixed 72 ms (nominal) time-out on power-up only, from por or brown-out detect. the power-up timer operates on an internal rc oscillator. the chip is kept in reset as long as pwrt is active. the pwrt delay allows the v dd to rise to an acceptable level. a configuration bit, pwrte can disable (if set) or enable (if cleared or programmed) the power-up timer. the power-up timer should always be enabled when brown-out detect is enabled. the power-up time delay will vary from chip to chip and due to: ?v dd variation ? temperature variation ? process variation see dc parameters for details ( section 13.0 ). 10.3.4 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over. this ensures that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. note: the por circuit does not produce an internal reset when v dd declines. v dd pic12f629/675 mclr r1 1 k ??? or greater ? c1 0.1 ? f (optional, not critical) ? 2003-2013 microchip technology inc. preliminary ds70091b-page 61 RFPIC12F675 10.3.5 brown-out detect (bod) the RFPIC12F675 members have on-chip brown-out detect circuitry. a configuration bit, boden, can disable (if clear/programmed) or enable (if set) the brown-out detect circuitry. if v dd falls below v bod for greater than parameter (t bod ) in table 13-4 (see section 13.0 ), the brown-out situation will reset the device. this will occur regardless of v dd slew-rate. a reset is not guaranteed to occur if v dd falls below v bod for less than parameter (t bod ). on any reset (power-on, brown-out, watchdog, etc.), the chip will remain in reset until v dd rises above bv dd (see figure 10-6 ). the power-up timer will now be invoked, if enabled, and will keep the chip in reset an additional 72 ms. if v dd drops below bv dd while the power-up timer is running, the chip will go back into a brown-out detect and the power-up timer will be re-initialized. once v dd rises above bv dd , the power-up timer will execute a 72 ms reset. figure 10-6: brown-o ut situations 10.3.6 time-out sequence on power-up, the time-out sequence is as follows: first, pwrt time-out is invoked after por has expired. then, ost is activated. the total time-out will vary based on oscillator configuration and pwrte bit status. for example, in ec mode with pwrte bit erased (pwrt disabled), there will be no time-out at all. figure 10-7 , figure 10-8 and figure 10-9 depict time-out sequences. since the time-outs occur from the por pulse, if mclr is kept low long enough, the time-outs will expire. then bringing mclr high will begin execution immediately (see figure 10-8 ). this is useful for testing purposes or to synchronize more than one RFPIC12F675 device operating in parallel. table 10-6 shows the reset conditions for some special registers, while table 10-7 shows the reset conditions for all the registers. 10.3.7 power control (pcon) status register the power control/status register, pcon (address 8eh) has two bits. bit0 is bod (brown-out). bod is unknown on power- on reset. it must then be set by the user and checked on subsequent resets to see if bod = 0, indicating that a brown-out has occurred. the bod status bit is a don?t care and is not necessarily predictable if the brown-out circuit is disabled (by setting boden bit = 0 in the configuration word). bit1 is por (power-on reset). it is a ?0? on power-on reset and unaffected otherwise. the user must write a ?1? to this bit following a power-on reset. on a subsequent reset, if por is ?0?, it will indicate that a power-on reset must have occurred (i.e., v dd may have gone too low). note: a brown-out detect does not enable the power-up timer if the pwrte bit in the configuration word is set. 72 ms (1) v bod v dd internal reset v bod v dd internal reset 72 ms (1) <72 ms 72 ms (1) v bod v dd internal reset note 1: 72 ms delay only if pwrte bit is programmed to ?0?. RFPIC12F675 ds70091b-page 62 preliminary ? 2003-2013 microchip technology inc. table 10-3: time-out in various situations table 10-4: status/pcon bits and their significance table 10-5: summary of regist ers associated with brown-out table 10-6: initialization condi tion for special registers oscillator configuration power-up brown-out detect wake-up from sleep pwrte = 0 pwrte = 1 pwrte = 0 pwrte = 1 xt, hs, lp t pwrt + 1024?t osc 1024?t osc t pwrt + 1024?t osc 1024?t osc 1024?t osc rc, ec, intosc t pwrt ? t pwrt ? ? por bod to pd 0 u 1 1 power-on reset 1 0 1 1 brown-out detect u u 0 u wdt reset u u 0 0 wdt wake-up u u u u mclr reset during normal operation u u 1 0 mclr reset during sleep legend: u = unchanged, x = unknown address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bod value on all other resets (1) 03h status irp rp1 rpo to pd z dc c 0001 1xxx 000q quuu 8eh pcon ? ? ? ? ? ? por bod ---- --0x ---- --uq legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ?0?, q = value depends on condition. note 1: other (non power-up) resets include mclr reset, brown-out detect and watchdog timer reset during normal operation. condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --0x mclr reset during normal operation 000h 000u uuuu ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 uuuu ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu brown-out detect 000h 0001 1uuu ---- --10 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ?0?. note 1: when the wake-up is due to an interrupt and global enable bit gie is set, the pc is loaded with the interrupt vector (0004h) after execution of pc+1. ? 2003-2013 microchip technology inc. preliminary ds70091b-page 63 RFPIC12F675 table 10-7: initialization condition for registers register address power-on reset ? mclr reset during ? normal operation ? mclr reset during sleep ? wdt reset ? brown-out detect (1) ? wake-up from sleep through interrupt ? wake-up from sleep through wdt time-out w ? xxxx xxxx uuuu uuuu uuuu uuuu indf 00h/80h ? ? ? tmr0 01h xxxx xxxx uuuu uuuu uuuu uuuu pcl 02h/82h 0000 0000 0000 0000 pc + 1 (3) status 03h/83h 0001 1xxx 000q quuu (4) uuuq quuu (4) fsr 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu gpio 05h --xx xxxx --uu uuuu --uu uuuu pclath 0ah/8ah ---0 0000 ---0 0000 ---u uuuu intcon 0bh/8bh 0000 0000 0000 000u uuuu uuqq (2) pir1 0ch 00-- 0--0 00-- 0--0 qq-- q--q (2,5) t1con 10h -000 0000 -uuu uuuu -uuu uuuu cmcon 19h -0-0 0000 -0-0 0000 -u-u uuuu adresh 1eh xxxx xxxx uuuu uuuu uuuu uuuu adcon0 1fh 00-- 0000 00-- 0000 uu-- uuuu option_reg 81h 1111 1111 1111 1111 uuuu uuuu trisio 85h --11 1111 --11 1111 --uu uuuu pie1 8ch 00-- 0--0 00-- 0--0 uu-- u--u pcon 8eh ---- --0x ---- --uu (1,6) ---- --uu osccal 90h 1000 00-- 1000 00-- uuuu uu-- wpu 95h --11 -111 --11 -111 uuuu uuuu ioc 96h --00 0000 --00 0000 --uu uuuu vrcon 99h 0-0- 0000 0-0- 0000 u-u- uuuu eedata 9ah 0000 0000 0000 0000 uuuu uuuu eeadr 9bh -000 0000 -000 0000 -uuu uuuu eecon1 9ch ---- x000 ---- q000 ---- uuuu eecon2 9dh ---- ---- ---- ---- ---- ---- adresl 9eh xxxx xxxx uuuu uuuu uuuu uuuu ansel 9fh -000 1111 -000 1111 -uuu uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ?0?, q = value depends on condition. note 1: if v dd goes too low, power-on reset will be activated and registers will be affected differently. 2: one or more bits in intcon and/or pir1 will be affected (to cause wake-up). 3: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 4: see table 10-6 for reset value for specific condition. 5: if wake-up was due to data eeprom write completing, bit 7 = 1; a/d conversion completing, bit 6 = 1; comparator input changing, bit 3 = 1; or timer1 rolling over, bit 0 = 1. all other interrupts generating a ? wake-up will cause these bits to = u. 6: if reset was due to brown-out, then bit 0 = 0. all other resets will cause bit 0 = u. RFPIC12F675 ds70091b-page 64 preliminary ? 2003-2013 microchip technology inc. figure 10-7: time-out sequence on power-up ( mclr not tied to v dd ): case 1 figure 10-8: time-out se quence on power-up ( mclr not tied to v dd ): case 2 figure 10-9: time-out se quence on power-up ( mclr tied to v dd ) t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset ? 2003-2013 microchip technology inc. preliminary ds70091b-page 65 RFPIC12F675 10.4 interrupts the RFPIC12F675 has 7 sources of interrupt: ? external interrupt gp2/int ? tmr0 overflow interrupt ? gpio change interrupts ? comparator interrupt ? a/d interrupt ? tmr1 overflow interrupt ? eeprom data write interrupt the interrupt control register (intcon) and peripheral interrupt register (pir) record individual interrupt requests in flag bits. the intcon register also has individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>) enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. individual interrupts can be disabled through their corresponding enable bits in intcon register and pie register. gie is cleared on reset. the return from interrupt instruction, retfie , exits interrupt routine, as well as sets the gie bit, which re-enables unmasked interrupts. the following interrupt flags are contained in the intcon register: ? int pin interrupt ? gp port change interrupt ? tmr0 overflow interrupt the peripheral interrupt flags are contained in the special register pir1. the corresponding interrupt enable bit is contained in special register pie1. the following interrupt flags are contained in the pir register: ? eeprom data write interrupt ? a/d interrupt ? comparator interrupt ? timer1 overflow interrupt when an interrupt is serviced: ? the gie is cleared to disable any further interrupt ? the return address is pushed onto the stack ? the pc is loaded with 0004h once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid gp2/ int recursive interrupts. for external interrupt events, such as the int pin, or gp port change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends upon when the interrupt event occurs (see figure 10-11 ). the latency is the same for one or two- cycle instructions. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. note 1: individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the gie bit. 2: when an instruction that clears the gie bit is executed, any interrupts that were pending for execution in the next cycle are ignored. the interrupts which were ignored are still pending to be serviced when the gie bit is set again. RFPIC12F675 ds70091b-page 66 preliminary ? 2003-2013 microchip technology inc. figure 10-10: interrupt logic tmr1if tmr1ie cmif cmie t0if t0ie intf inte gpif gpie gie peie wake-up (if in sleep mode) interrupt to cpu eeie eeif adif adie ioc-gp0 ioc0 ioc-gp1 ioc1 ioc-gp2 ioc2 ioc-gp3 ioc3 ioc-gp4 ioc4 ioc-gp5 ioc5 ? 2003-2013 microchip technology inc. preliminary ds70091b-page 67 RFPIC12F675 10.4.1 gp2/int interrupt external interrupt on gp2/int pin is edge-triggered; either rising if intedg bit (option<6>) is set, of falling, if intedg bit is clear. when a valid edge appears on the gp2/int pin, the intf bit (intcon<1>) is set. this interrupt can be disabled by clearing the inte control bit (intcon<4>). the intf bit must be cleared in software in the interrupt service routine before re-enabling this interrupt. the gp2/int interrupt can wake-up the processor from sleep if the inte bit was set prior to going into sleep. the status of the gie bit decides whether or not the processor branches to the interrupt vector following wake-up. see section 10.9 for details on sleep and figure 10-13 for timing of wake-up from sleep through gp2/int interrupt. 10.4.2 tmr0 interrupt an overflow (ffh ? 00h) in the tmr0 register will set the t0if (intcon<2>) bit. the interrupt can be enabled/disabled by setting/clearing t0ie (intcon<5>) bit. for operation of the timer0 module, see section 4.0 . 10.4.3 gpio interrupt an input change on gpio change sets the gpif (intcon<0>) bit. the interrupt can be enabled/ disabled by setting/clearing the gpie (intcon<3>) bit. plus individual pins can be configured through the ioc register. 10.4.4 comparator interrupt see section 6.9 for description of comparator interrupt. 10.4.5 a/d converter interrupt after a conversion is complete, the adif flag (pir<6>) is set. the interrupt can be enabled/disabled by setting or clearing adie (pie<6>). see section 7.0 for operation of the a/d converter interrupt. figure 10-11: int pin interrupt timing note: the ansel (9fh) and cmcon (19h) registers must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ?0?. note: if a change on the i/o pin should occur when the read operation is being executed (start of the q2 cycle), then the gpif inter - rupt flag may not get set. q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed interrupt latency pc pc+1 pc+1 0004h 0005h inst (0004h) inst (0005h) dummy cycle inst (pc) inst (pc+1) inst (pc-1) inst (0004h) dummy cycle inst (pc) ? 1 4 5 1 2 3 note 1: intf flag is sampled here (every q1). 2: asynchronous interrupt latency = 3-4 t cy . synchronous latency = 3 t cy , where t cy = instruction cycle time. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: clkout is available only in rc oscillator mode. 4: for minimum width of int pulse, refer to ac specs. 5: intf is enabled to be set any time during the q4-q1 cycles. RFPIC12F675 ds70091b-page 68 preliminary ? 2003-2013 microchip technology inc. table 10-8: summary of interrupt registers 10.5 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key registers during an interrupt, (e.g., w register and status register). this must be implemented in software. example 10-2 stores and restores the status and w registers. the user register, w_temp, must be defined in both banks and must be defined at the same offset from the bank base address (i.e., w_temp is defined at 0x20 in bank 0 and it must also be defined at 0xa0 in bank 1). the user register, status_temp, must be defined in bank 0. the example 10-2 : ? stores the w register ? stores the status register in bank 0 ? executes the isr code ? restores the status (and bank select bit register) ? restores the w register example 10-2: saving the status and w registers in ram 10.6 watchdog timer (wdt) the watchdog timer is a free running, on-chip rc oscillator, which requires no external components. this rc oscillator is separate from the external rc oscillator of the clkin pin and intosc. that means that the wdt will run, even if the clock on the osc1 and osc2 pins of the device has been stopped (for example, by execution of a sleep instruction). during normal operation, a wdt time-out generates a device reset. if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation. the wdt can be permanently disabled by programming the configuration bit wdte as clear ( section 10.1 ). 10.6.1 wdt period the wdt has a nominal time-out period of 18 ms, (with no prescaler). the time-out periods vary with tempera - ture, v dd and process variations from part to part (see dc specs). if longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt under software control by writing to the option register. thus, time-out periods up to 2.3 seconds can be realized. the clrwdt and sleep instructions clear the wdt and the prescaler, if assigned to the wdt, and prevent it from timing out and generating a device reset. the to bit in the status register will be cleared upon a watchdog timer time-out. 10.6.2 wdt programming considerations it should also be taken in account that under worst case conditions (i.e., v dd = min., temperature = max., max. wdt prescaler) it may take several seconds before a wdt time-out occurs. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bod value on all other resets 0bh, 8bh intcon gie peie t0ie inte gpie t0if intf gpif 0000 0000 0000 000u 0ch pir1 eeif adif ? ? cmif ? ? tmr1if 00-- 0--0 00-- 0--0 8ch pie1 eeie adie ? ? cmie ? ? tmr1ie 00-- 0--0 00-- 0--0 legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. ? shaded cells are not used by the interrupt module. movwf w_temp ;copy w to temp register, could be in either bank swapf status,w ;swap status to be saved into w bcf status,rp0 ;change to bank 0 regardless of current bank movwf status_temp ;save status to bank 0 register : :(isr) : swapf status_temp,w;swap status_temp register into w, sets bank to original state movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w ? 2003-2013 microchip technology inc. preliminary ds70091b-page 69 RFPIC12F675 figure 10-12: watchdo g timer block diagram table 10-9: summary of watchdog timer registers 10.7 id locations four memory locations (2000h-2003h) are designated as id locations where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution but are readable and writable during program/verify. only the least significant 7 bits of the id locations are used. 10.8 code protection if the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. t0cki t0se pin clkout tmr0 watchdog timer wdt time-out ps0 - ps2 wdte data bus set flag bit t0if on overflow t0cs note 1: t0se, t0cs, psa, ps0-ps2 are bits in the option register. 0 1 0 1 0 1 sync 2 cycles 8 8 8-bit prescaler 0 1 (= f osc /4) psa psa psa address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bod value on all other resets 81h option_reg gppu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 2007h config. bits cp boden mclre pwrte wdte f0sc2 f0sc1 f0sc0 uuuu uuuu uuuu uuuu legend: u = unchanged, shaded cells are not used by the watchdog timer. note: the entire data eeprom and flash program memory will be erased when the code protection is turned off. the intosc calibration data is also erased. see RFPIC12F675 programming specification for more information. RFPIC12F675 ds70091b-page 70 preliminary ? 2003-2013 microchip technology inc. 10.9 power-down mode (sleep) the power-down mode is entered by executing a sleep instruction. if the watchdog timer is enabled: ? wdt will be cleared but keeps running ? pd bit in the status register is cleared ? to bit is set ? oscillator driver is turned off ? i/o ports maintain the status they had before sleep was executed (driving high, low, or ? hi-impedance). for lowest current consumption in this mode, all i/o pins should be either at v dd , or v ss , with no external circuitry drawing current from the i/o pin and the comparators and cv ref should be disabled. i/o pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribu - tion from on-chip pull-ups on gpio should be considered. the mclr pin must be at a logic high level (v ihmc ). 10.9.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin 2. watchdog timer wake-up (if wdt was enabled) 3. interrupt from gp2/int pin, gpio change, or a peripheral interrupt. the first event will cause a device reset. the two latter events are considered a continuation of program execution. the to and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. to bit is cleared if wdt wake-up occurred. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the correspond - ing interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction, then branches to the interrupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have an nop after the sleep instruction. the wdt is cleared when the device wakes up from sleep, regardless of the source of wake-up. figure 10-13: wake-up from sleep through interrupt note: it should be noted that a reset generated by a wdt time-out does not drive mclr pin low. note: if the global interrupts are disabled (gie is cleared), but any interrupt source has both its interrupt enable bit and the correspond - ing interrupt flag bits set, the device will immediately wake-up from sleep. the sleep instruction is completely executed. q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout (4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale). approximately 1 ? s delay will be there for rc osc mode. see section 12 for wake-up from sleep delay in intosc mode. 3: gie = '1' assumed. in this case after wake-up, the processor jumps to the interrupt routine. if gie = '0', execution will conti nue in-line. 4: clkout is not available in xt, hs, lp or ec osc modes, but shown here for timing reference. ? 2003-2013 microchip technology inc. preliminary ds70091b-page 71 RFPIC12F675 figure 10-14: typical in-circuit serial programming connection 10.10 in-circuit serial programming the RFPIC12F675 microcontrollers can be serially programmed while in the end application circuit. this is done with two lines for clock and data, and three lines for power, ground, and programming voltage. this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller before shipping the product. this also allows the most recent firmware or custom firmware to be programmed. the device is placed into a program/verify mode by holding the gp0 and gp1 pins low, while raising the mclr (v pp ) pin from v il to v ihh (see programming specification). gp0 becomes the programming data and gp1 becomes the programming clock. both gp0 and gp1 are schmitt trigger inputs in this mode. after reset, to place the device into programming/ verify mode, the program counter (pc) is at location 00h. a 6-bit command is then supplied to the device. depending on the command, 14-bits of program data are then supplied to or from the device, depending on whether the command was a load or a read. for complete details of serial programming, please refer to the programming specifications document. a typical in-circuit serial programming connection is shown in figure 10-14 . the programming connections are isolated from conflicting outputs and capacitive loads by the 3 resistors. the v dd connection on mclr may not be required if the pin is configured as gp3. do not place sensitive circuitry on the gp3/ mclr pin without protection since the v pp signal goes well above v dd during programming. figure 10-15: parallel dip socket for emulation 10.11 in-circuit debugging since in-circuit debugging requires the loss of clock, data and mclr pins, mplab ? icd 2 development with an 8-pin microcontroller is not practical. since the mplab ice 2000 emulation module leads would be too long for the rf signals the following debug/emula - tion strategy is recommended. build a prototype board with all your digital, analog, and rf circuitry. add an 8 pin dip socket for the pic12f675 debugging. connect the socket as shown in figure 10- 15 . when soldering the RFPIC12F675 down bend up pins 1-4 and 17-20 so that they do not contact the board. a pic12f675 or emulation/debugging develop - ment tool can be plugged into the socket as in figure 10-16 . this test method encourages rf development to start early, as soon as the firmware can toggle the rf enable and data lines. the socket can even be left in the final layout for in-circuit production programming. a simple method for programming is to solder all the RFPIC12F675 pins to the board and move the 8-pin dip socket to the back side of the board. then use the 8-pin standoff from the mplab ice 2000 emulator to connect the pcb to a programmer such as the pro mate ? ii or pickit? 1 as in figure 10-17 . there is an icd 2 header inteface board for the pic12f675, part number ac162050. this special icd module is mounted on the top of a header and its external connector signals to n o r m a l connections to n o r m a l connections RFPIC12F675 v dd v ss gp3/mclr /v pp gp1 gp0 +5v 0v v pp clk data i/o v dd 1 2 3 4 8 7 6 5 v ss gp0 gp1 gp2 v dd gp5 gp4 gp3 pic12f675 RFPIC12F675 RFPIC12F675 ds70091b-page 72 preliminary ? 2003-2013 microchip technology inc. signals are routed to the mplab icd 2 connector. on the bottom of the header is an 8-pin socket that plugs into the user?s target via the 8-pin standoff connector. when the icd pin on the pic12f675-icd device is held low, the in-circuit debugger functionality is enabled. this function allows simple debugging functions when used with mplab icd 2. when the microcontroller has this feature enabled, some of the resources are not available for general use. table 10-10 shows resources consumed by the background debugger: table 10-10: debugger resources for more information, see 8-pin mplab icd 2 header information sheet (ds51292) available on microchip?s website (www.microchip.com). figure 10-16: in-circuit debuggin g using the parallel dip socket figure 10-17: in-circuit programmi ng using the parallel dip socket i/o pins icdclk, icddata stack 1 level program memory address 0h must be nop 300h - 3feh socket dva12xp081 standoff RFPIC12F675 to mplab ice 2000 pcm12xb0 or ac162050 standoff RFPIC12F675 socket programmer ? 2003-2013 microchip technology inc. preliminary ds70091b-page 73 RFPIC12F675 11.0 instruction set summary the RFPIC12F675 instruction set is highly orthogonal and is comprised of three basic categories: ? byte-oriented operations ? bit-oriented operations ? literal and control operations each RFPIC12F675 instruction is a 14-bit word divided into an opcode, which specifies the instruction type, and one or more operands, which further specify the operation of the instruction. the formats for each of the categories is presented in figure 11-1 , while the various opcode fields are summarized in table 11-1 . table 11-2 lists the instructions recognized by the mpasm tm assembler. a complete description of each instruction is also available in the pic mid- range reference manual (ds33023). for byte-oriented instructions, ? f ? represents a file register designator and ? d ? represents a destination designator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ? d ? is zero, the result is placed in the w register. if ? d ? is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ? b ? represents a bit field designator, which selects the bit affected by the operation, while ? f ? represents the address of the file in which the bit is located. for literal and control operations, ? k ? represents an 8-bit or 11-bit constant, or literal value. one instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 mhz, this gives a normal instruction execution time of 1 ? s. all instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. when this occurs, the execution takes two instruction cycles, with the second cycle executed as a nop . all instruction examples use the format ?0xhh? to represent a hexadecimal number, where ?h? signifies a hexadecimal digit. 11.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (r-m-w) operation. the register is read, the data is modified, and the result is stored according to either the instruc - tion, or the destination designator ?d?. a read operation is performed on a register even if the instruction writes to that register. for example, a clrf gpio instruction will read gpio, clear all the data bits, then write the result back to gpio. this example would have the unintended result that the condition that sets the gpif flag would be cleared. table 11-1: opcode field descriptions figure 11-1: general format for instructions note: to maintain upward compatibility with future products, do not use the option and trisio instructions. field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for ? compatibility with all microchip software tools. d destination select; d = 0 : store result in w, d = 1: store result in file register f. default is d = 1. pc program counter to time-out bit pd power-down bit byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only RFPIC12F675 ds70091b-page 74 preliminary ? 2003-2013 microchip technology inc. table 11-2: RFPIC12F675 instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to , pd z to , pd c,dc,z z note 1: when an i/o register is modified as a function of itself (e.g., movf gpio , 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . note: additional information on the mid-range instruction set is available in the pic mid-range mcu family ref - erence manual (ds33023). ? 2003-2013 microchip technology inc. preliminary ds70091b-page 75 RFPIC12F675 11.2 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 ? k ? 255 operation: (w) + k ? (w) status affected: c, dc, z description: the contents of the w register are added to the eight-bit literal 'k' and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 ? f ? 127 d ??????? operation: (w) + (f) ? (destination) status affected: c, dc, z description: add the contents of the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in ? register 'f'. andlw and literal with w syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (w) .and. (k) ? (w) status affected: z description: the contents of w register are and?ed with the eight-bit literal 'k'. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 ? f ? 127 d ??????? operation: (w) .and. (f) ? (destination) status affected: z description: and the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 0 ? (f) status affected: none description: bit 'b' in register 'f' is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 1 ? (f) status affected: none description: bit 'b' in register 'f' is set. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 ? f ? 127 0 ? b < 7 operation: skip if (f) = 1 status affected: none description: if bit 'b' in register 'f' is '0', the next instruction is executed. if bit 'b' is '1', then the next ? instruction is discarded and a nop is executed instead, making this a 2t cy instruction. btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: skip if (f) = 0 status affected: none description: if bit 'b' in register 'f' is '1', the next instruction is executed. if bit 'b', in register 'f', is '0', the next instruction is discarded, and a nop is executed instead, making this a 2t cy instruction. RFPIC12F675 ds70091b-page 76 preliminary ? 2003-2013 microchip technology inc. call call subroutine syntax: [ label ] call k operands: 0 ? k ? 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<4:3>) ? pc<12:11> status affected: none description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven-bit immedi - ate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 ? f ? 127 operation: 00h ? (f) 1 ? z status affected: z description: the contents of register 'f' are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? to 1 ? pd status affected: to , pd description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. ? status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 ? f ? 127 d ? [0,1] operation: ( f ) ? (destination) status affected: z description: the contents of register 'f' are complemented. if 'd' is 0, the result is stored in w. if 'd' is 1, the result is stored back in register 'f'. decf decrement f syntax: [ label ] decf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) - 1 ? (destination) status affected: z description: decrement register 'f'. if 'd' is 0, the result is stored in the w ? register. if 'd' is 1, the result is stored back in register 'f'. ? 2003-2013 microchip technology inc. preliminary ds70091b-page 77 RFPIC12F675 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) - 1 ? (destination); skip if result = 0 status affected: none description: the contents of register 'f' are decremented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in ? register 'f'. if the result is 1, the next instruc - tion is executed. if the result is 0, then a nop is executed instead, making it a 2t cy instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 2047 operation: k ? pc<10:0> pclath<4:3> ? pc<12:11> status affected: none description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two- cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) + 1 ? (destination) status affected: z description: the contents of register 'f' are incremented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in ? register 'f'. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) + 1 ? (destination), ? skip if result = 0 status affected: none description: the contents of register 'f' are incremented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in ? register 'f'. if the result is 1, the next instruc - tion is executed. if the result is 0, a nop is executed instead, making it a 2t cy instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (w) .or. k ? (w) status affected: z description: the contents of the w register are or?ed with the eight-bit literal 'k'. the result is placed in the w ? register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (w) .or. (f) ? (destination) status affected: z description: inclusive or the w register with register 'f'. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in ? register 'f'. RFPIC12F675 ds70091b-page 78 preliminary ? 2003-2013 microchip technology inc. movf move f syntax: [ label ] movf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) ? (destination) status affected: z description: the contents of register f are moved to a destination dependant upon the status of d. if d = 0, ? destination is w register. if d = 1, the destination is file register f itself. d = 1 is useful to test a file register, since status flag z is affected. movlw move literal to w syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? (w) status affected: none description: the eight-bit literal 'k' is loaded into w register. the don?t cares will assemble as 0?s. movwf move w to f syntax: [ label ] movwf f operands: 0 ? f ? 127 operation: (w) ? (f) status affected: none description: move data from w register to ? register 'f'. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc, 1 ? gie status affected: none retlw return with literal in w syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? (w); tos ? pc status affected: none description: the w register is loaded with the eight-bit literal 'k'. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. ? 2003-2013 microchip technology inc. preliminary ds70091b-page 79 RFPIC12F675 rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 ? f ? 127 d ? [0,1] operation: see description below status affected: c description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is stored back in register 'f'. return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 ? f ? 127 d ? [0,1] operation: see description below status affected: c description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in ? register 'f'. register f c register f c sleep syntax: [ label ] sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? to , 0 ? pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. sublw subtract w from literal syntax: [ label ] sublw k operands: 0 ?? k ?? 255 operation: k - (w) ??? w) status affected: c, dc, z description: the w register is subtracted (2?s complement method) from the eight-bit literal 'k'. the result is placed in the w register. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 ?? f ?? 127 d ? [0,1] operation: (f) - (w) ??? destination) status affected: c, dc, z description: subtract (2?s complement method) w register from register 'f'. if 'd' is 0, the result is stored in the w ? register. if 'd' is 1, the result is stored back in register 'f'. RFPIC12F675 ds70091b-page 80 preliminary ? 2003-2013 microchip technology inc. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f<3:0>) ? (destination<7:4>), (f<7:4>) ? (destination<3:0>) status affected: none description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed in register 'f'. xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ??? w) status affected: z description: the contents of the w register are xor?ed with the eight-bit literal 'k'. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (w) .xor. (f) ??? destination) status affected: z description: exclusive or the contents of the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. ? 2003-2013 microchip technology inc. preliminary ds70091b-page1-81 RFPIC12F675 12.0 development support the pic ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ ? mplib tm object librarian - mplab c30 c compiler - mplab asm30 assembler/linker/library ? simulators - mplab sim software simulator - mplab dspic30 software simulator ?emulators - mplab ice 2000 in-circuit emulator - mplab ice 4000 in-circuit emulator ? in-circuit debugger - mplab icd 2 ? device programmers -pro mate ? ii universal device programmer - picstart ? plus development programmer ? low cost demonstration boards - picdem tm 1 demonstration board - picdem.net tm demonstration board - picdem 2 plus demonstration board - picdem 3 demonstration board - picdem 4 demonstration board - picdem 17 demonstration board - picdem 18r demonstration board - picdem lin demonstration board - picdem usb demonstration board ? evaluation kits -k ee l oq ? - picdem msc -microid ? -can - powersmart ? -analog 12.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. the mplab ide is a windows ? based application that contains: ? an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high level source code debugging ? mouse over variable inspection ? extensive on-line help the mplab ide allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to pic mcu emulator and simulator tools (automatically updates all project information) ? debug using: - source files (assembly or c) - absolute listing file (mixed assembly and c) - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increasing flexibility and power. 12.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all pic mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol ref - erence, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process RFPIC12F675 ds70091b-page 1-82 preliminary ? 2003-2013 microchip technology inc. 12.3 mplab c17 and mplab c18 ? c compilers the mplab c17 and mplab c18 code development systems are complete ansi c compilers for microchip?s pic17cxxx and pic18cxxx family of microcontrollers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 12.4 mplink object linker/ ? mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can link relocatable objects from pre-compiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of pre-compiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 12.5 mplab c30 c compiler the mplab c30 c compiler is a full-featured, ansi compliant, optimizing compiler that translates standard ansi c programs into dspic30f assembly language source. the compiler also supports many command- line options and language extensions to take full advantage of the dspic30f device hardware capabili - ties, and afford fine control of the compiler code generator. mplab c30 is distributed with a complete ansi c standard library. all library functions have been validated and conform to the ansi c library standard. the library includes functions for string manipulation, dynamic memory allocation, data conversion, timekeeping, and math functions (trigonometric, exponential and hyperbolic). the compiler provides symbolic information for high level source debugging with the mplab ide. 12.6 mplab asm30 assembler, linker, and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 compiler uses the assembler to produce it?s object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire dspic30f instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility 12.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc hosted environment by simulating the pic series microcontrollers on an instruction level. on any given instruction, the data areas can be exam - ined or modified and stimuli can be applied from a file, or user defined key press, to any pin. the execution can be performed in single-step, execute until break, or trace mode. the mplab sim simulator fully supports symbolic debugging using the mplab c17 and mplab c18 c compilers, as well as the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. 12.8 mplab sim30 software simulator the mplab sim30 software simulator allows code development in a pc hosted environment by simulating the dspic30f series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. the mplab sim30 simulator fully supports symbolic debugging using the mplab c30 c compiler and mplab asm30 assembler. the simulator runs in either a command line mode for automated tasks, or from mplab ide. this high speed simulator is designed to debug, analyze and optimize time intensive dsp routines. ? 2003-2013 microchip technology inc. preliminary ds70091b-page1-83 RFPIC12F675 12.9 mplab ice 2000 ? high performance universal ? in-circuit emulator the mplab ice 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for pic microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator system with enhanced trace, trigger and data monitor - ing features. interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new pic microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 12.10 mplab ice 4000 ? high performance universal ? in-circuit emulator the mplab ice 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high- end pic microcontrollers. software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab icd 4000 is a premium emulator system, providing the features of mplab ice 2000, but with increased emulation memory and high speed perfor - mance for dspic30f and pic18xxxx devices. its advanced emulator features include complex triggering and timing, up to 2 mb of emulation memory, and the ability to view variables in real-time. the mplab ice 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft windows 32-bit operating system were cho - sen to best make these features available in a simple, unified application. 12.11 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low cost, run-time development tool, connecting to the host pc via an rs-232 or high speed usb interface. this tool is based on the flash pic mcus and can be used to develop for these and other pic microcontrollers. the mplab icd 2 utilizes the in- circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost effective in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by setting breakpoints, single- stepping and watching variables, cpu status and peripheral registers. running at full speed enables test - ing hardware and applications in real-time. mplab icd 2 also serves as a development programmer for selected pic devices. 12.12 pro mate ii universal device programmer the pro mate ii is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features an lcd display for instructions and error messages and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify, and program pic devices without a pc connection. it can also set code protection in this mode. 12.13 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low cost, prototype programmer. it connects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most pic devices up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. RFPIC12F675 ds70091b-page 1-84 preliminary ? 2003-2013 microchip technology inc. 12.14 picdem 1 pic mcu ? demonstration board the picdem 1 demonstration board demonstrates the capabilities of the pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the sample microcontrollers provided with the picdem 1 demonstration board can be programmed with a pro mate ii device program - mer, or a picstart plus development programmer. the picdem 1 demonstration board can be connected to the mplab ice in-circuit emulator for testing. a prototype area extends the circuitry for additional application components. features include an rs-232 interface, a potentiometer for simulated analog input, push button switches and eight leds. 12.15 picdem.net internet/ethernet demonstration board the picdem.net demonstration board is an internet/ ethernet demonstration board using the pic18f452 microcontroller and tcp/ip firmware. the board supports any 40-pin dip device that conforms to the standard pinout used by the pic16f877 or pic18c452. this kit features a user friendly tcp/ip stack, web server with html, a 24l256 serial eeprom for xmodem download to web pages into serial eeprom, icsp/mplab icd 2 interface connector, an ethernet interface, rs-232 interface, and a 16 x 2 lcd display. also included is the book and cd-rom ?tcp/ip lean, web servers for embedded systems,? by jeremy bentham 12.16 picdem 2 plus ? demonstration board the picdem 2 plus demonstration board supports many 18-, 28-, and 40-pin microcontrollers, including pic16f87x and pic18fxx2 devices. all the neces - sary hardware and software is included to run the dem - onstration programs. the sample microcontrollers provided with the picdem 2 demonstration board can be programmed with a pro mate ii device program - mer, picstart plus development programmer, or mplab icd 2 with a universal programmer adapter. the mplab icd 2 and mplab ice in-circuit emulators may also be used with the picdem 2 demonstration board to test firmware. a prototype area extends the circuitry for additional application components. some of the features include an rs-232 interface, a 2 x 16 lcd display, a piezo speaker, an on-board temperature sensor, four leds, and sample pic18f452 and pic16f877 flash microcontrollers. 12.17 picdem 3 pic16c92x demonstration board the picdem 3 demonstration board supports the pic16c923 and pic16c924 in the plcc package. all the necessary hardware and software is included to run the demonstration programs. 12.18 picdem 4 8/14/18-pin demonstration board the picdem 4 can be used to demonstrate the capa - bilities of the 8-, 14-, and 18-pin pic16xxxx and pic18xxxx mcus, including the pic16f818/819, pic16f87/88, pic16f62xa and the pic18f1320 family of microcontrollers. picdem 4 is intended to showcase the many features of these low pin count parts, including lin and motor control using eccp. special provisions are made for low power operation with the supercapacitor circuit, and jumpers allow on- board hardware to be disabled to eliminate current draw in this mode. included on the demo board are pro - visions for crystal, rc or canned oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, db-9 rs-232 interface, icd connector for programming via icsp and development with mplab icd 2, 2x16 liquid crystal display, pcb footprints for h- bridge motor driver, lin transceiver and eeprom. also included are: header for expansion, eight leds, four potentiometers, three push buttons and a proto - typing area. included with the kit is a pic16f627a and a pic18f1320. tutorial firmware is included along with the user?s guide. 12.19 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. a programmed sample is included. the pro mate ii device programmer, or the picstart plus develop - ment programmer, can be used to reprogram the device for user tailored application development. the picdem 17 demonstration board supports program download and execution from external on-board flash memory. a generous prototype area is available for user hardware expansion. ? 2003-2013 microchip technology inc. preliminary ds70091b-page1-85 RFPIC12F675 12.20 picdem 18r pic18c601/801 demonstration board the picdem 18r demonstration board serves to assist development of the pic18c601/801 family of microchip microcontrollers. it provides hardware implementation of both 8-bit multiplexed/de-multiplexed and 16-bit memory modes. the board includes 2 mb external flash memory and 128 kb sram memory, as well as serial eeprom, allowing access to the wide range of memory types supported by the pic18c601/801. 12.21 picdem lin pic16c43x demonstration board the powerful lin hardware and software kit includes a series of boards and three pic microcontrollers. the small footprint pic16c432 and pic16c433 are used as slaves in the lin communication and feature on- board lin transceivers. a pic16f874 flash micro - controller serves as the master. all three microcon - trollers are programmed with firmware to provide lin bus communication. 12.22 pickit tm 1 flash starter kit a complete "development system in a box", the pickit flash starter kit includes a convenient multi-section board for programming, evaluation, and development of 8/14-pin flash pic ? microcontrollers. powered via usb, the board operates under a simple windows gui. the pickit 1 starter kit includes the user's guide (on cd rom), pickit 1 tutorial software and code for vari - ous applications. also included are mplab ? ide (inte - grated development environment) software, software and hardware "tips 'n tricks for 8-pin flash pic ? microcontrollers" handbook and a usb interface cable. supports all current 8/14-pin flash pic microcontrollers, as well as many future planned devices. 12.23 picdem usb pic16c7x5 demonstration board the picdem usb demonstration board shows off the capabilities of the pic16c745 and pic16c765 usb microcontrollers. this board provides the basis for future usb products. 12.24 evaluation and ? programming tools in addition to the picdem series of circuits, microchip has a line of evaluation kits and demonstration software for these products. ?k ee l oq evaluation and programming tools for microchip?s hcs secure data products ? can developers kit for automotive network applications ? analog design boards and filter design software ? powersmart battery charging evaluation/ ? calibration kits ?irda ? development kit ? microid development and rflab tm development software ? seeval ? designer kit for memory evaluation and endurance calculations ? picdem msc demo boards for switching mode power supply, high power ir driver, delta sigma adc, and flow rate sensor check the microchip web page and the latest product line card for the complete list of demonstration and evaluation kits. RFPIC12F675 ds70091b-page 1-86 preliminary ? 2003-2013 microchip technology inc. notes: ? 2003-2013 microchip technology inc. preliminary ds70091b-page 87 RFPIC12F675 13.0 electrical specifications absolute maximum ratings? ambient temperature under bias................................................................................................. .......... -40 to +125c storage temperature ............................................................................................................ ............ -65c to +150c voltage on v dd with respect to v ss ....................................................................................................... -0.3 to +6.5v voltage on v ddrf with respect to v ssrf ................................................................................................ -0.3 to +7.0v voltage on mclr with respect to vss...................................................................................................-0.3 to +13.5v voltage on all gpio pins with respect to v ss ............................................................................ -0.3v to (v dd + 0.3v) voltage on all other rf transmitter pins with respect to v ssrf .............................................-0.3v to (v ddrf + 0.3v) total power dissipation (1) ............................................................................................................................... 800 mw maximum current out of v ss pin ..................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................ 250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ??????????????????????????????????????????????????????????????? ?????????????????????????????????????????????????? 20 ma output clamp current, i ok (vo < 0 or vo >v dd ) ??????????????????????????????????????????????????????????????? ???????????????????????????????????????????? 20 ma maximum output current sunk by any gpio pin .................................................................................... ........... 25 ma maximum output current sourced by any gpio pin ................................................................................. ......... 25 ma maximum total current sunk by all gpio pins .................................................................................... ............. 125 ma maximum total current sourced all gpio pins.................................................................................... ............. 125 ma note 1: power dissipation is calculated as follows: ? p dis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v ol x i ol ) + v ddrf x {i ddrf - ? i ohrf } + ? {(v ddrf - v ohrf ) x i ohrf } + ? (v olrf x i olrf ) ? ? notice : stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latchup. thus, a series resistor of 50-100 ? should be used when applying a "low" level to the mclr pin, rather than pulling this pin directly to v ss . RFPIC12F675 ds70091b-page 88 preliminary ? 2003-2013 microchip technology inc. figure 13-1: RFPIC12F675 with a/d di sabled voltage-frequency graph, ? -40c ? t a ? +125c figure 13-2: RFPIC12F675 with a/d enabled voltage-frequency graph, ? -40c ? t a ? +125c 5.5 2.0 3.5 2.5 0 3.0 4.0 4.5 5.0 4 microcontroller frequency (mhz) v dd (volts) note 1: the shaded region indicates the permissible combinations of voltage and frequency. 816 12 20 10 5.5 2.0 3.5 2.5 0 3.0 4.0 4.5 5.0 4 microcontroller frequency (mhz) v dd (volts) note 1: the shaded region indicates the permissible combinations of voltage and frequency. 816 12 20 10 ? 2003-2013 microchip technology inc. preliminary ds70091b-page 89 RFPIC12F675 figure 13-3: rfpic 12f675 with a/d enabled voltage-frequency graph, ? 0c ? t a ? +125c 5.5 2.0 3.5 2.5 0 3.0 4.0 4.5 5.0 4 microcontroller frequency (mhz) v dd (volts) note 1: the shaded region indicates the permissible combinations of voltage and frequency. 816 12 20 10 2.2 RFPIC12F675 ds70091b-page 90 preliminary ? 2003-2013 microchip technology inc. 13.1 dc characteristics: RFPIC12F675-i (industrial), RFPIC12F675-e (extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym characteristic min typ? max units conditions d001 d001a d001b d001c d001d v dd supply voltage 2.0 2.2 2.5 3.0 4.5 ? ? ? ? ? 5.5 5.5 5.5 5.5 5.5 v v v v v f osc < = 4 mhz: RFPIC12F675 with a/d off RFPIC12F675 with a/d on, 0c to +125c RFPIC12F675 with a/d on, -40c to +125c 4 mh z < f osc < = 10 mhz f osc > 10 mhz d002 v dr ram data retention ? voltage (1) 1.5* ? ? v device in sleep mode d003 v por v dd start voltage to ensure internal power-on reset signal ? v ss ? v see section on power-on reset for details d004 s vdd v dd rise rate to ensure ? internal power-on reset ? signal 0.05* ? ? v/ms see section on power-on reset for details d005 v bod ? 2.1 ? v d006 d006a d006b d006c v ddrf rf transmitter supply voltage 2.0 3.0 4.0 5.0 ? ? ? ? 5.5 5.5 5.5 5.5 v v v v output power = 4 dbm output power = 7.5 dbm output power = 8.5 dbm output power = 9 dbm d007 v lvd rf low voltage disable 1.8 1.85 1.9 v t a ? +23c, rfen = v ddrf * these parameters are characterized but not tested. ? data in "typ" column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. ? 2003-2013 microchip technology inc. preliminary ds70091b-page 91 RFPIC12F675 13.2 dc characteristics: RFPIC12F675-i (industrial) standard operating conditions (unless otherwise stated) operating temperature -40 ? c ? t a ? +85 ? c for industrial param no. device characteristics min typ? max units conditions v dd note d010 supply current (i dd ) (3) ? 9 16 ? a 2.0 f osc = 32 khz lp oscillator mode ? 18 28 ? a 3.0 ? 34 54 ? a 5.0 d011 ? 110 150 ? a 2.0 f osc = 1 mhz xt oscillator mode ? 190 280 ? a 3.0 ? 330 450 ? a 5.0 d012 ? 220 280 ? a 2.0 f osc = 4 mhz xt oscillator mode ? 370 650 ? a 3.0 ? 0.6 1.4 ma 5.0 d013 ? 70 110 ? a 2.0 f osc = 1 mhz ec oscillator mode ? 140 250 ? a 3.0 ? 260 390 ? a 5.0 d014 ? 180 250 ? a 2.0 f osc = 4 mhz ec oscillator mode ? 320 470 ? a 3.0 ? 580 850 ? a 5.0 d015 ? 340 450 ? a 2.0 f osc = 4 mhz intosc mode ? 500 700 ? a 3.0 ? 0.8 1.1 ma 5.0 d016 ? 180 250 ? a 2.0 f osc = 4 mhz extrc mode ? 320 450 ? a 3.0 ? 580 800 ? a 5.0 d017 ? 2.1 2.95 ma 4.5 f osc = 20 mhz hs oscillator mode ? 2.4 3.0 ma 5.0 ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. 3: total device current is the sum of i dd from v dd and i ddrf from v ddrf . RFPIC12F675 ds70091b-page 92 preliminary ? 2003-2013 microchip technology inc. 13.3 dc characteristics: RFPIC12F675-i (industrial) standard operating conditions (unless otherwise stated) operating temperature -40 ? c ? t a ? +85 ? c for industrial param no. device characteristics min typ? max units conditions v dd note d020 power-down current (i pd ) (3) ? 0.99 700 n a 2.0 wdt, bod, comparators, v ref , and t1osc disabled ? 1.2 770 n a 3.0 ? 2.9 995 n a 5.0 d021 ? 0.3 1.5 ? a 2.0 wdt current (1) ? 1.8 3.5 ? a 3.0 ? 8.4 17 ? a 5.0 d022 ? 58 70 ? a 3.0 bod current (1) ? 109 130 ? a 5.0 d023 ? 3.3 6.5 ? a 2.0 comparator current (1) ? 6.1 8.5 ? a 3.0 ? 11.5 16 ? a 5.0 d024 ? 58 70 ? a 2.0 cv ref current (1) ? 85 100 ? a 3.0 ? 138 160 ? a 5.0 d025 ? 4.0 6.5 ? a 2.0 t1 o sc current (1) ? 4.6 7.0 ? a 3.0 ? 6.0 10.5 ? a 5.0 d026 ? 1.2 775 n a 3.0 a/d current (1) ? 2.2 1.0 m a 5.0 d027 power-down rf current (i pdrf ) (3) ? 0.050 tbd ? a 3.0 rf transmitter with rfen=0 ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral ? current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 2: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd . 3: total device current is the sum of i pd from v dd and i pdrf from v ddrf . ? 2003-2013 microchip technology inc. preliminary ds70091b-page 93 RFPIC12F675 13.4 dc characteristics: rf pic12f675 -e (extended) standard operating conditions (unless otherwise stated) operating temperature -40 ? c ? t a ? +125 ? c for extended param no. device characteristics min typ? max units conditions v dd note d010e supply current (i dd ) (3) ? 9 16 ? a 2.0 f osc = 32 khz lp oscillator mode ? 18 28 ? a 3.0 ? 35 54 ? a 5.0 d011e ? 110 150 ? a 2.0 f osc = 1 mhz xt oscillator mode ? 190 280 ? a 3.0 ? 330 450 ? a 5.0 d012e ? 220 280 ? a 2.0 f osc = 4 mhz xt oscillator mode ? 370 650 ? a 3.0 ? 0.6 1.4 ma 5.0 d013e ? 70 110 ? a 2.0 f osc = 1 mhz ec oscillator mode ? 140 250 ? a 3.0 ? 260 390 ? a 5.0 d014e ? 180 250 ? a 2.0 f osc = 4 mhz ec oscillator mode ? 320 470 ? a 3.0 ? 580 850 ? a 5.0 d015e ? 340 450 ? a 2.0 f osc = 4 mhz intosc mode ? 500 780 ? a 3.0 ? 0.8 1.1 ma 5.0 d016e ? 180 250 ? a 2.0 f osc = 4 mhz extrc mode ? 320 450 ? a 3.0 ? 580 800 ? a 5.0 d017e ? 2.1 2.95 ma 4.5 f osc = 20 mhz hs oscillator mode ? 2.4 3.0 ma 5.0 ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. 3: total device current is the sum of i dd from v dd and i ddrf from v ddrf . RFPIC12F675 ds70091b-page 94 preliminary ? 2003-2013 microchip technology inc. 13.5 dc characteristics: rf pic12f675 -e (extended) standard operating conditions (unless otherwise stated) operating temperature -40 ? c ? t a ? +125 ? c for extended param no. device characteristics min typ? max units conditions v dd note d020e power-down current (i pd ) (3) ? 0.0011 3.5 ? a 2.0 wdt, bod, comparators, v ref , and t1osc disabled ? 0.0012 4.0 ? a 3.0 ? 0.0022 8.0 ? a 5.0 d021e ? 0.3 6.0 ? a 2.0 wdt current (1) ? 1.8 9.0 ? a 3.0 ? 8.4 20 ? a 5.0 d022e ? 58 70 ? a 3.0 bod current (1) ? 109 130 ? a 5.0 d023e ? 3.3 10 ? a 2.0 comparator current (1) ? 6.1 13 ? a 3.0 ? 11.5 24 ? a 5.0 d024e ? 58 70 ? a 2.0 cv ref current (1) ? 85 100 ? a 3.0 ? 138 165 ? a 5.0 d025e ? 4.0 10 ? a 2.0 t1 o sc current (1) ? 4.6 12 ? a 3.0 ? 6.0 20 ? a 5.0 d026e ? 0.0012 6.0 ? a 3.0 a/d current (1) ? 0.0022 8.5 ? a 5.0 d027e power-down rf current (i pdrf ) (3) ? 0.050 tbd ? a 3.0 rf transmitter, rfen=v ssrf ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral ? current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 2: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd . 3: total device current is the sum of i pd from v dd and i pdrf from v ddrf . ? 2003-2013 microchip technology inc. preliminary ds70091b-page 95 RFPIC12F675 13.6 dc characteristics: rf pic12f675 k 13.7 dc characteristics: rf pic12f675 f 13.8 dc characteristics: rf pic12f675 h standard operating conditions (unless otherwise stated) operating temperature t a ? +23 ? c operating frequency f c = 315 mhz param no. device characteristics min typ max units conditions v dd note d018a rf transmitter current (i ddrf ) (2) 2.0 2.7 5.0 ma 3.0 power step 0, rfen=data ask =1 d018b 2.9 3.5 7.0 ma 3.0 power step 1, rfen=data ask =1 d018c 3.2 4.7 7.9 ma 3.0 power step 2, rfen=data ask =1 d018d 4.5 6.5 11 ma 3.0 power step 3, rfen=data ask =1 d018e 7.0 10.7 16 ma 3.0 power step 4, rfen=data ask =1 note 1: the supply current is mainly a function of the operating voltage and frequency. other factors such as output loading and temperature also have an impact on the current consumption. 2: total device current is the sum of i dd from v dd and i ddrf from v ddrf . standard operating conditions (unless otherwise stated) operating temperature t a ? +23 ? c operating frequency f c = 434 mhz param no. device characteristics min typ max units conditions v dd note d018a rf transmitter current (i ddrf ) (2) 2.0 2.7 5.0 ma 3.0 power step 0, rfen=data ask =1 d018b 2.9 3.5 7.0 ma 3.0 power step 1, rfen=data ask =1 d018c 3.2 4.7 7.9 ma 3.0 power step 2, rfen=data ask =1 d018d 4.5 6.5 11 ma 3.0 power step 3, rfen=data ask =1 d018e 7.0 10.7 16 ma 3.0 power step 4, rfen=data ask =1 note 1: the supply current is mainly a function of the operating voltage and frequency. other factors such as output loading and temperature also have an impact on the current consumption. 2: total device current is the sum of i dd from v dd and i ddrf from v ddrf . standard operating conditions (unless otherwise stated) operating temperature t a ? +23 ? c operating frequency f c = 868 mhz param no. device characteristics min typ max units conditions v dd note d018a rf transmitter current (i ddrf ) (2) 2.6 4.0 6.5 ma 3.0 power step 0, rfen=data ask =1 d018b 3.5 5.3 8.5 ma 3.0 power step 1, rfen=data ask =1 d018c 4.5 6.7 11 ma 3.0 power step 2, rfen=data ask =1 d018d 6.0 9.0 14 ma 3.0 power step 3, rfen=data ask =1 d018e 9.0 14.0 20 ma 3.0 power step 4, rfen=data ask =1 note 1: the supply current is mainly a function of the operating voltage and frequency. other factors such as output loading and temperature also have an impact on the current consumption. 2: total device current is the sum of i dd from v dd and i ddrf from v ddrf . RFPIC12F675 ds70091b-page 96 preliminary ? 2003-2013 microchip technology inc. 13.9 dc characteristics: RFPIC12F675-i (industrial), RFPIC12F675-e (extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym characteristic min typ? max units conditions input low voltage v il i/o ports d030 with ttl buffer v ss ? 0.8 v 4.5v ? v dd ? 5.5v d030a v ss ? 0.15 v dd v otherwise d031 with schmitt trigger buffer v ss ? 0.2 v dd v entire range d032 mclr , osc1 (rc mode) v ss ? 0.2 v dd v d033 osc1 (xt and lp modes) v ss ? 0.3 v (note 1) d033a osc1 (hs mode) v ss ? 0.3 v dd v (note 1) d034 data ask , data fsk , rfen v ss ? 0.3 v ddrf v input high voltage v ih i/o ports ? d040 d040a with ttl buffer 2.0 (0.25 v dd + 0.8) ? ? v dd v dd v v 4.5v ? v dd ?? 5.5v otherwise d041 with schmitt trigger buffer 0.8 v dd ? v dd entire range d042 mclr 0.8 v dd ? v dd v d043 osc1 (xt and lp modes) 1.6 ? v dd v (note 1) d043a osc1 (hs mode) 0.7 v dd ? v dd v (note 1) d043b osc1 (rc mode) 0.9 v dd ? v dd v d044 data ask , data fsk , rfen 0.7 v dd ? v ddrf v d070 i pur gpio weak pull-up current 50* 250 400* ? a v dd = 5.0v, v pin = v ss d071 data ask weak pull-up 0.1* 1.5 12* ? a v ddrf = rfen = 3.0v d072 rfen in weak pull-down 0.2* 2.0 20* ? a v ddrf = rfen = 3.0v input leakage current (3) d060 i il gpio ports, data ask , data fsk , rfen ? ?? 0 ? 1 ?? 1 ? a v ss ?? v pin ?? v dd , ? pin at hi-impedance d060a analog inputs ? ?? 0 ? 1 ?? 1 ? a v ss ?? v pin ?? v dd d060b v ref ? ?? 0 ? 1 ?? 1 ? a v ss ?? v pin ?? v dd d061 mclr (2) ? ?? 0 ? 1 ?? 5 ? a v ss ?? v pin ?? v dd d063 osc1 ? ?? 0 ? 1 ?? 5 ? a v ss ?? v pin ?? v dd , xt, hs and ? lp osc configuration output low voltage d080 v ol i/o ports ? ? 0.6 v i ol = 8.5 ma, v dd = 4.5v (ind.) d083 osc2/clkout (rc mode) ? ? 0.6 v i ol = 1.6 ma, v dd = 4.5v (ind.) i ol = 1.2 ma, v dd = 4.5v (ext.) output high voltage d090 v oh i/o ports v dd - 0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v (ind.) d092 osc2/clkout (rc mode) v dd - 0.7 ? ? v i oh = -1.3 ma, v dd = 4.5v (ind.) i oh = -1.0 ma, v dd = 4.5v (ext.) * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended to use an external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage cu rrent may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. ? 2003-2013 microchip technology inc. preliminary ds70091b-page 97 RFPIC12F675 13.10 dc characteristics: RFPIC12F675-i (i ndustrial), rfpic12f 675-e (extended) (cont.) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym characteristic min typ? max units conditions capacitive loading specs on output pins d100 c osc2 osc2 pin ? ? 15* pf in xt, hs and lp modes when external clock is used to drive osc1 d101 c io all i/o pins ? ? 50* pf data eeprom memory d120 e d byte endurance 100k 1m ? e/w -40 ? c ? t a ?? +85c d120a e d byte endurance 10k 100k ? e/w +85c ? t a ?? +125c d121 v drw v dd for read/write v min ? 5.5 v using eecon to read/write v min = minimum operating ? voltage d122 t dew erase/write cycle time ? 5 6 ms d123 t retd characteristic retention 40 ? ? year provided no other specifications are violated d124 t ref number of total erase/write cycles before refresh (1) 1m 10m ? e/w -40 ? c ? t a ?? +85c program flash memory d130 e p cell endurance 10k 100k ? e/w -40 ? c ? t a ?? +85c d130a e d cell endurance 1k 10k ? e/w +85c ? t a ?? +125c d131 v pr v dd for read v min ? 5.5 v v min = minimum operating ? voltage d132 v pew v dd for erase/write 4.5 ? 5.5 v d133 t pew erase/write cycle time ? 2 2.5 ms d134 t retd characteristic retention 40 ? ? year provided no other specifications are violated rf transmitter (2) d150 r on fsk switch on resistance ? 20 60 ? data fsk =0, rfen=1 d151 r off fsk switch off resistance 1 ? ? m ? data fsk =1, rfen=1 d152a d152b d152c d152d d152e v ps rf power select ? voltage v ssrf 0.14 0.28 0.57 1.23 ? ? ? ? ? 0.1 0.24 0.51 1.18 v ddrf v v v v v power level step 0 power level step 1 power level step 2 power level step 3 power level step 4 d153 i ps power select current 6 8 11 ? a rfen=1 * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: see section 8.5.1 for additional information. 2: these limits are tested at room temperature. RFPIC12F675 ds70091b-page 98 preliminary ? 2003-2013 microchip technology inc. 13.11 timing parameter symbology the timing parameter symbols have been created with one of the following formats: figure 13-4: load conditions 1. tpps2pps 2. tpps t f frequency ttime lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) vvalid llow z hi-impedance v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins 15 pf for osc2 output load condition 1 load condition 2 ? 2003-2013 microchip technology inc. preliminary ds70091b-page 99 RFPIC12F675 13.12 ac characteristics: RFPIC12F675 (industrial, extended) figure 13-5: exter nal clock timing table 13-1: external clock timing requirements param no. sym characteristic min typ? max units conditions f osc external clkin frequency (1) dc ? 37 khz lp osc mode dc ? 4 mhz xt mode dc ? 20 mhz hs mode dc ? 20 mhz ec mode oscillator frequency (1) 5 ? 37 khz lp osc mode ? 4 ? mhz intosc mode dc ? 4 mhz rc osc mode 0.1 ? 4 mhz xt osc mode 1 ? 20 mhz hs osc mode 1 t osc external clkin period (1) 27 ? ? ? s lp osc mode 50 ? ? ns hs osc mode 50 ? ? ns ec osc mode 250 ? ? ns xt osc mode oscillator period (1) 27 200 ? s lp osc mode ? 250 ? ns intosc mode 250 ? ? ns rc osc mode 250 ? 10,000 ns xt osc mode 50 ? 1,000 ns hs osc mode 2 t cy instruction cycle time (1) 200 t cy dc ns t cy = 4/f osc 3 to sl , to sh external clkin (osc1) high external clkin low 2* ? ? ? s lp oscillator, t osc l/h duty cycle 20* ? ? ns hs oscillator, t osc l/h duty cycle 100 * ? ? ns xt oscillator, t osc l/h duty cycle 4 to sr , to sf external clkin rise external clkin fall ? ? 50* ns lp oscillator ? ? 25* ns xt oscillator ? ? 15* ns hs oscillator * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min? values with an external clock applied to osc1 pin. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 RFPIC12F675 ds70091b-page 100 preliminary ? 2003-2013 microchip technology inc. table 13-2: precision internal oscillator parameters param no. sym characteristic freq tolerance min typ? max units conditions f10 f osc internal calibrated intosc frequency ? 1 3.96 4.00 4.04 mhz v dd = 3.5v, 25 ? c ? 2 3.92 4.00 4.08 mhz 2.5v ?? v dd ? 5.5v 0 ? c ? t a ? +85 ? c ? 5 3.80 4.00 4.20 mhz 2.0v ?? v dd ? 5.5v -40 ? c ? t a ? +85 ? c (ind) -40 ? c ? t a ? +125 ? c (ext) f14 t iosc st oscillator wake-up from sleep start-up time* ? ? 6 8 ? s v dd = 2.0v, -40 ? c to +85 ? c ? ? 4 6 ? s v dd = 3.0v, -40 ? c to +85 ? c ? ? 3 5 ? s v dd = 5.0v, -40 ? c to +85 ? c * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. ? 2003-2013 microchip technology inc. preliminary ds70091b-page 101 RFPIC12F675 figure 13-6: clkout and i/o timing table 13-3: clkout and i/o timing requirements osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 22 23 19 18 15 11 12 16 old value new value param no. sym characteristic min typ? max units conditions 10 tosh2ckl osc1 ? to clk - out ? ? 75 200 ns (note 1) 11 tosh2ckh osc1 ? to clk - out ? ? 75 200 ns (note 1) 12 tc k r clkout rise time ? 35 100 ns (note 1) 13 tc k f clkout fall time ? 35 100 ns (note 1) 14 tc k l 2 i o v clkout ? to port out valid ? ? 20 ns (note 1) 15 tiov2ckh port in valid before clkout ? t osc + 200 ns ? ? ns (note 1) 16 tc k h 2 i o i port in hold after clkout ? 0 ? ? ns (note 1) 17 to s h 2 i o v osc1 ? (q1 cycle) to port out valid ? 50 150 * ns ? ? 300 ns 18 to s h 2 i o i osc1 ? (q2 cycle) to port input invalid (i/o in hold time) 100 ? ? ns 19 tiov2osh port input valid to osc1 ?? ? (i/o in setup time) 0 ? ? ns 20 tior port output rise time ? 10 40 ns 21 tiof port output fall time ? 10 40 ns 22 tinp int pin high or low time 25 ? ? ns 23 trbp gpio change int high or low time t cy ? ? ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. note 1: measurements are taken in rc mode where clkout output is 4xt osc . RFPIC12F675 ds70091b-page 102 preliminary ? 2003-2013 microchip technology inc. figure 13-7: reset, watchdog timer, oscillator start-up timer and ? power-up timer timing figure 13-8: brown-out dete ct timing and characteristics v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 b vdd reset (due to bod) v dd (device in brown-out detect) (device not in brown-out detect) 72 ms time-out (1) 35 note 1: 72 ms delay only if pwrte bit in configuration word is programmed to ?0?. ? 2003-2013 microchip technology inc. preliminary ds70091b-page 103 RFPIC12F675 table 13-4: reset, watchdog timer, oscill ator start-up timer, power-up timer, and brown-out detect requirements param no. sym characteristic min typ? max units conditions 30 t mc l mclr pulse width (low) 2 tbd ? tbd ? tbd ? s ms v dd = 5v, -40c to +85c extended temperature 31 t wdt watchdog timer time-out period (no prescaler) 10 10 17 17 25 30 ms ms v dd = 5v, -40c to +85c extended temperature 32 t ost oscillation start-up timer period ? 1024t osc ? ? t osc = osc1 period 33* t pwrt power-up timer period 28* tbd 72 tbd 132* tbd ms ms v dd = 5v, -40c to +85c extended temperature 34 t ioz i/o hi-impedance from mclr low or watchdog timer reset ? ? 2.0 ? s b vdd brown-out detect voltage 2.025 ? 2.175 v brown-out hysteresis tbd ? ? ? 35 t bod brown-out detect pulse width 100* ? ? ? s v dd ? b vdd (d005) * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. RFPIC12F675 ds70091b-page 104 preliminary ? 2003-2013 microchip technology inc. figure 13-9: timer0 and time r1 external clock timings table 13-5: timer0 and timer1 external clock requirements t0cki t1cki 40 41 42 45 46 47 48 tmr0 or tmr1 param no. sym characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ? ns with prescaler 10 ? ? ns 41* tt0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ? ns with prescaler 10 ? ? ns 42* tt0p t0cki period greater of: 20 or t cy + 40 n ? ? ns n = prescale value (2, 4, ..., 256) 45* tt1h t1cki high time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns 46* tt1l t1cki low time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns 47* tt1p t1cki input period synchronous greater of: 30 or t cy + 40 n ? ? ns n = prescale value (1, 2, 4, 8) asynchronous 60 ? ? ns ft1 timer1 oscillator input frequency range ? (oscillator enabled by setting bit t1oscen) dc ? 200* khz 48 tckeztmr1 delay from external clock edge to timer increment 2 t osc * ? 7 t osc * ? * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are ? not tested. ? 2003-2013 microchip technology inc. preliminary ds70091b-page 105 RFPIC12F675 table 13-6: comparator specifications table 13-7: comparator voltage reference specifications comparator specifications standard operating conditions ? -40c to +125c (unless otherwise stated) sym characteristics min typ max units comments v os input offset voltage ? ? 5.0 ? 10 mv v cm input common mode voltage 0 ? v dd - 1.5 v c mrr common mode rejection ratio +55* ? ? db t rt response time (1) ? 150 400* ns t mc 2 co v comparator mode change to output valid ? ? 10* ? s * these parameters are characterized but not tested. note 1: response time measured with one comparator input at (v dd - 1.5)/2 while the other input transitions from v ss to v dd - 1.5v. voltage reference specifications standard operating conditions ? -40c to +125c (unless otherwise stated) sym characteristics min typ max units comments resolution ? ? v dd /24* v dd /32 ? ? lsb lsb low range (vrr = 1) high range (vrr = 0) absolute accuracy ? ? ? ? ? 1/2 ?? 1/2* lsb lsb low range (vrr = 1) ? high range (vrr = 0) unit resistor value (r) ? 2k* ? ? settling time (1) ? ? 10* ? s * these parameters are characterized but not tested. note 1: settling time measured while vrr = 1 and vr<3:0> transitions from 0000 to 1111 . RFPIC12F675 ds70091b-page 106 preliminary ? 2003-2013 microchip technology inc. table 13-8: RFPIC12F675 a/d converter characteristics : param no. sym characteristic min typ? max units conditions a01 n r resolution ? ? 10 bits bit a02 e abs total absolute error* ? ? ? 1 lsb v ref = 5.0v a03 e il integral error ? ? ? 1 lsb v ref = 5.0v a04 e dl differential error ? ? ? 1 lsb no missing codes to 10 bits v ref = 5.0v a05 e fs full scale range 2.2* ? 5.5* v a06 e off offset error ? ? ? 1 lsb v ref = 5.0v a07 e gn gain error ? ? ? 1 ls b v ref = 5.0v a10 ? monotonicity ? guaranteed (3) ? ? v ss ? v ain ? v ref + a20 a20a v ref reference voltage 2.0 2.5 ? ? v dd + 0.3 v absolute minimum to ensure 10-bit accuracy a21 v ref reference v high (v dd or v ref ) v ss ? v dd v a25 v ain analog input ? voltage v ss ? v ref v a30 z ain recommended impedance of ? analog voltage source ? ? 10 k ? a50 i ref v ref input ? current (2) 10 ? ? ? 1000 10 ? a ? a during v ain acquisition. ? based on differential of v hold to v ain . ? during a/d conversion cycle. * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from external v ref or v dd pin, whichever is selected as reference input. 3: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. ? 2003-2013 microchip technology inc. preliminary ds70091b-page 107 RFPIC12F675 figure 13-10: RFPIC12F675 a/d conv ersion timing (normal mode) table 13-9: RFPIC12F675 a/d conversion requirements 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 987 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy 6 134 (t osc /2) (1) 1 t cy param no. sym characteristic min typ? max units conditions 130 t ad a/d clock period 1.6 ? ? ? s t osc based, v ref ?? 3.0v 3.0* ? ? ? s t osc based, v ref full range 130 t ad a/d internal rc oscillator period 3.0* 6.0 9.0* ? s adcs<1:0> = 11 (rc mode) at v dd = 2.5v 2.0* 4.0 6.0* ? s at v dd = 5.0v 131 t cnv conversion time (not including acquisition time) (1) ? 11 ? t ad set go bit to new data in a/d result register 132 t acq acquisition time (note 2) 5* 11.5 ? ? ? ? s ? s the minimum time is the amplifier settling time. this may be used if the ?new? input voltage has not changed by more than 1 lsb (i.e., 4.1 mv @ 4.096v) from the last sampled voltage (as stored on c hold ). 134 t go q4 to a/d clock start ? t osc /2 ? ? if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 7.1 for minimum conditions. RFPIC12F675 ds70091b-page 108 preliminary ? 2003-2013 microchip technology inc. figure 13-11: RFPIC12F675 a/d conv ersion timing (sleep mode) table 13-10: RFPIC12F675 a/d conver sion requirements (sleep mode) param no. sym characteristic min typ? max units conditions 130 t ad a/d clock period 1.6 ? ? ? s v ref ?? 3.0v 3.0* ? ? ? s v ref full range 130 t ad a/d internal rc oscillator period 3.0* 6.0 9.0* ? s adcs<1:0> = 11 (rc mode) at v dd = 2.5v 2.0* 4.0 6.0* ? s at v dd = 5.0v 131 t cnv conversion time (not including acquisition time) (1) ? 11 ? t ad 132 t acq acquisition time (note 2) 5* 11.5 ? ? ? ? s ? s the minimum time is the amplifier settling time. this may be used if the ?new? input voltage has not changed by more than 1 lsb (i.e., 4.1 mv @ 4.096v) from the last sampled voltage (as stored on c hold ). 134 t go q4 to a/d clock start ? t osc /2 + t cy ? ? if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 7.1 for minimum conditions. 131 130 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 9 7 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 134 6 8 132 1 t cy (t osc /2 + t cy ) (1) 1 t cy ? 2003-2013 microchip technology inc. preliminary ds70091b-page 109 RFPIC12F675 table 13-11: RFPIC12F675k rf trans mitter specifications (315 mhz) rf transmitter specifications standard operating conditions ? t a = +23c (unless otherwise stated) v ddrf = 3.0v (unless otherwise stated) f c = 315 mhz (unless otherwise stated) sym characteristics min typ max units comments f c vco frequency 290 ? 350 mhz 32 x f rfxtal f xtal crystal frequency 9.06 ? 10.94 mhz fundamental mode f ref reference frequency 2.265 ? 2.735 mhz f rfxtal / 4 c l load capacitance 10 ? 15 pf c o static capacitance ? ? 7 pf r s series resistance ? ? 70 ? a spur spurious response ? ? -10 db for fsk operation ? f vdd frequency stability vs v ddrf ? ? ? 3 ppm ? f ta frequency stability vs temp ? ? ? 10 ppm crystal temp constant ? f fsk deviation ? 5 ? ? 80 khz depends on crystal parameters r fsk fsk data rate ? ? 40 kbit/s nrz r ask ask data rate ? ? 40 kbit/s nrz t on rfen high to transmit ? 1.2 1.5 ms p off rf output power in step 0 ? ? -70 dbm rfen=1 p 1 rf output power in step 1 ? -12 ? dbm rfen=1 p 2 rf output power in step 2 ? -4 ? dbm rfen=1 p 3 rf output power in step 3 ? 2 ? dbm rfen=1 p 4 rf output power in step 4 ? 4 ? dbm rfen=1, v ddrf =2.0v ? 7.5 ? dbm rfen=1, v ddrf =3.0v ? 8.5 9.5 dbm rfen=1, v ddrf =4.0v ? 9.0 10.5 dbm rfen=1, v ddrf =5.0v l(f m ) phase noise ? -86 ? dbc/hz 200 khz offset p spur spurious emissions ? ? -54 dbm 47 mhz < f < 74 mh z 87.5 mhz < f < 118 mh z 174 mhz < f < 230 mh z 470 mhz < f < 862 mh z rbw = 100 khz ? ? -36 dbm f < 1 gh z rbw = 100 khz ? ? -30 dbm f > 1 gh z rbw = 1 mhz RFPIC12F675 ds70091b-page 110 preliminary ? 2003-2013 microchip technology inc. table 13-12: rfpic 12f675f rf transmitter sp ecifications (434 mhz) rf transmitter specifications standard operating conditions ? t a = +23c (unless otherwise stated) v ddrf = 3.0v (unless otherwise stated) f c = 433.92 mhz (unless otherwise stated) sym characteristics min typ max units comments f c vco frequency 380 ? 450 mhz 32 x f rfxtal f xtal crystal frequency 11.88 ? 14.06 mhz fundamental mode f ref reference frequency 2.97 ? 3.515 mhz f rfxtal / 4 c l load capacitance 10 ? 15 pf c o static capacitance ? ? 7 pf r s series resistance ? ? 70 ? a spur spurious response ? ? -10 db for fsk operation ? f vdd frequency stability vs v ddrf ? ? ? 3 ppm ? f ta frequency stability vs temp ? ? ? 10 ppm crystal temp constant ? f fsk deviation ? 5 ? ? 80 khz depends on crystal parameters r fsk fsk data rate ? ? 40 kbit/s nrz r ask ask data rate ? ? 40 kbit/s nrz t on rfen high to transmit ? 0.8 1.2 ms p off rf output power in step 0 ? ? -70 dbm rfen=1 p 1 rf output power in step 1 ? -12 ? dbm rfen=1 p 2 rf output power in step 2 ? -4 ? dbm rfen=1 p 3 rf output power in step 3 ? 2 ? dbm rfen=1 p 4 rf output power in step 4 ? 4 ? dbm rfen=1, v ddrf =2.0v ? 7.5 ? dbm rfen=1, v ddrf =3.0v ? 8.5 9.5 dbm rfen=1, v ddrf =4.0v ? 9.0 10.5 dbm rfen=1, v ddrf =5.0v l(f m ) phase noise ? -86 ? dbc/hz 200 khz offset p spur spurious emissions ? ? -54 dbm 47 mhz < f < 74 mh z 87.5 mhz < f < 118 mh z 174 mhz < f < 230 mh z 470 mhz < f < 862 mh z rbw = 100 khz ? ? -36 dbm f < 1 gh z rbw = 100 khz ? ? -30 dbm f > 1 gh z rbw = 1 mhz ? 2003-2013 microchip technology inc. preliminary ds70091b-page 111 RFPIC12F675 table 13-13: rfpic 12f675h rf transmitter specifications (868/915 mhz) rf transmitter specifications standard operating conditions ? t a = +23c (unless otherwise stated) v ddrf = 3.0v (unless otherwise stated) f c = 868.3 mhz (unless otherwise stated) sym characteristics min typ max units comments f c vco frequency 850 ? 930 mhz 32 x f rfxtal f xtal crystal frequency 26.56 ? 29.06 mhz fundamental mode f ref reference frequency 3.32 ? 3.63 mhz f rfxtal / 8 c l load capacitance 10 ? 15 pf c o static capacitance ? ? 7 pf r s series resistance ? ? 50 ? a spur spurious response ? ? -10 db for fsk operation ? f vdd frequency stability vs v ddrf ? ? ? 3 ppm ? f ta frequency stability vs temp ? ? ? 10 ppm crystal temp constant ? f fsk deviation ? 5 ? ? 80 khz depends on crystal parameters r fsk fsk data rate ? ? 40 kbit/s nrz r ask ask data rate ? ? 40 kbit/s nrz t on rfen high to transmit ? 0.6 1.0 ms p off rf output power in step 0 ? ? -70 dbm rfen=1 p 1 rf output power in step 1 ? -12 ? dbm rfen=1 p 2 rf output power in step 2 ? -4 ? dbm rfen=1 p 3 rf output power in step 3 ? 2 ? dbm rfen=1 p 4 rf output power in step 4 ? 4 ? dbm rfen=1, v ddrf =2.0v ? 7.5 ? dbm rfen=1, v ddrf =3.0v ? 8.5 9.5 dbm rfen=1, v ddrf =4.0v ? 9.0 10.5 dbm rfen=1, v ddrf =5.0v l(f m ) phase noise ? -82 ? dbc/hz 200 khz offset p spur spurious emissions ? ? -54 dbm 47 mhz < f < 74 mh z 87.5 mhz < f < 118 mh z 174 mhz < f < 230 mh z 470 mhz < f < 862 mh z rbw = 100 khz ? ? -36 dbm f < 1 gh z rbw = 100 khz ? ? -30 dbm f > 1 gh z rbw = 1 mhz RFPIC12F675 ds70091b-page 112 preliminary ? 2003-2013 microchip technology inc. notes: ? 2003-2013 microchip technology inc. preliminary ds70091b-page 113 RFPIC12F675 14.0 dc and ac characteristics graphs and tables the graphs and tables provided in this section are for design guidance and are not tested . in some graphs or tables, the data presented are outside specified operating range (i.e., outside specified v dd range). this is for information only and devices are ensured to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'typical' represents the mean of the distribution at 25c. 'max' or 'min' represents (mean + 3 ? ) or (mean - 3 ? ) respectively, where ? is standard deviation, over the whole temperature range. figure 14-1: typical i pd vs. v dd over temp (-40c to +25c) figure 14-2: typical i pd vs. v dd over temp (+85c) typical baseline i pd 0.0e+00 1.0e-09 2.0e-09 3.0e-09 4.0e-09 5.0e-09 6.0e-09 2 2.5 3 3.5 4 4.5 5 5.5 v dd ( v ) i pd (a) -40 0 25 typical baseline i pd 0.0e+00 5.0e-08 1.0e-07 1.5e-07 2.0e-07 2.5e-07 3.0e-07 3.5e-07 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (a) 85 RFPIC12F675 ds70091b-page 114 preliminary ? 2003-2013 microchip technology inc. figure 14-3: typical i pd vs. v dd over temp (+125c) figure 14-4: maximum i pd vs. v dd over temp (-40c to +25c) typical baseline i pd 0.0e+00 5.0e-07 1.0e-06 1.5e-06 2.0e-06 2.5e-06 3.0e-06 3.5e-06 4.0e-06 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (a) 125 maximum baseline i pd 0.0e+00 1.0e-08 2.0e-08 3.0e-08 4.0e-08 5.0e-08 6.0e-08 7.0e-08 8.0e-08 9.0e-08 1.0e-07 22.533.544.555.5 v dd (v) i pd ( a ) -40 0 25 ? 2003-2013 microchip technology inc. preliminary ds70091b-page 115 RFPIC12F675 figure 14-5: maximum i pd vs. v dd over temp (+85c) figure 14-6: maximum i pd vs. v dd over temp (+125c) maximum baseline i pd 0.0e+00 1.0e-07 2.0e-07 3.0e-07 4.0e-07 5.0e-07 6.0e-07 7.0e-07 8.0e-07 9.0e-07 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (a) 85 maximum baseline i pd 0.0e+00 1.0e-06 2.0e-06 3.0e-06 4.0e-06 5.0e-06 6.0e-06 7.0e-06 8.0e-06 9.0e-06 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (a) 125 RFPIC12F675 ds70091b-page 116 preliminary ? 2003-2013 microchip technology inc. figure 14-7: typical i pd with bod enabled vs. v dd over temp (-40c to +125c) figure 14-8: typical i pd with cmp enabled vs. v dd over temp (-40c to +125c) typical bod i pd 50 60 70 80 90 100 110 120 130 33.544.555.5 v dd (v) i pd (ua) -40 0 25 85 125 typical comparator i pd 0.0e+00 2.0e-06 4.0e-06 6.0e-06 8.0e-06 1.0e-05 1.2e-05 1.4e-05 1.6e-05 1.8e-05 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (a) -40 0 25 85 125 ? 2003-2013 microchip technology inc. preliminary ds70091b-page 117 RFPIC12F675 figure 14-9: typical i pd with a/d enabled vs. v dd over temp (-40c to +25c) figure 14-10: typical i pd with a/d enabled vs. v dd over temp (+85c) typical a/d i pd 0.0e+00 5.0e-10 1.0e-09 1.5e-09 2.0e-09 2.5e-09 3.0e-09 3.5e-09 4.0e-09 4.5e-09 5.0e-09 2 2.5 3 3.5 4 4.5 5 5.5 v dd (v) i pd (a) -40 0 25 typical a/d i pd 0.0e+00 5.0e-08 1.0e-07 1.5e-07 2.0e-07 2.5e-07 3.0e-07 3.5e-07 2 2.5 3 3.5 4 4.5 5 5.5 v dd (v) i pd ( a ) 85 RFPIC12F675 ds70091b-page 118 preliminary ? 2003-2013 microchip technology inc. figure 14-11: typical i pd with a/d enabled vs. v dd over temp (+125c) figure 14-12: typical i pd with t1 osc enabled vs. v dd over temp (-40c to +125c), 32 khz, c1 and c2=50 pf) typical a/d i pd 0.0e+00 5.0e-07 1.0e-06 1.5e-06 2.0e-06 2.5e-06 3.0e-06 3.5e-06 22.533.544.555.5 v dd (v) i pd (a) 125 typical t1 i pd 0.00e+00 2.00e-06 4.00e-06 6.00e-06 8.00e-06 1.00e-05 1.20e-05 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (a) -40 0 25 85 125 ? 2003-2013 microchip technology inc. preliminary ds70091b-page 119 RFPIC12F675 figure 14-13: typical i pd with cv ref enabled vs. v dd over temp (-40c to +125c) figure 14-14: typical i pd with wdt enabled vs. v dd over temp (-40c to +125c) typical c v ref i pd 40 60 80 100 120 140 160 2 2.5 3 3.5 4 4.5 5 5.5 v dd (v) i pd (ua) -40 0 25 85 125 typical wdt i pd 0 2 4 6 8 10 12 14 16 2 2.5 3 3.5 4 4.5 5 5.5 v dd ( v ) i pd (ua) -40 0 25 85 125 RFPIC12F675 ds70091b-page 120 preliminary ? 2003-2013 microchip technology inc. figure 14-15: maximum and minimum ? intosc freq vs. temperature with 0.1 ? f and 0.01 ? f decoupling (v dd = 3.5v) figure 14-16: maximum and minimum ? intosc freq vs. v dd with 0.1 ? f and 0.01 ? f decoupling (+25c) internal oscillator frequency vs temperature 3.80e+06 3.85e+06 3.90e+06 3.95e+06 4.00e+06 4.05e+06 4.10e+06 4.15e+06 4.20e+06 -40c 0c 25c 85c 125c temperature (c) frequency (hz) -3sigma average +3sigma internal oscillator frequency vs v dd 3.80e+06 3.85e+06 3.90e+06 3.95e+06 4.00e+06 4.05e+06 4.10e+06 4.15e+06 4.20e+06 2.0v 2.5v 3.0v 3.5v 4.0v 4.5v 5.0v 5.5v v dd (v) fre q uenc y ( hz ) -3sigma average +3sigma ? 2003-2013 microchip technology inc. preliminary ds70091b-page 121 RFPIC12F675 figure 14-17: typical wdt period vs. v dd (-40 ? c to +125 ? c) wdt time-out 0 5 10 15 20 25 30 35 40 45 50 2 2.5 3 3.5 4 4.5 5 5.5 v dd (v) time ( ms) -40 0 25 85 125 RFPIC12F675 ds70091b-page 122 preliminary ? 2003-2013 microchip technology inc. notes: ? 2003-2013 microchip technology inc. preliminary ds70091b-page 123 RFPIC12F675 15.0 packaging information 15.1 package marking information 20-lead ssop xxxxxxxxxxx xxxxxxxxxxx yywwnnn rfpic? 12f675h 0314cbp example legend: xx...x customer-specific information ? y year code (last digit of calendar year) ? yy year code (last 2 digits of calendar year) ? ww week code (week of january 1 is week ?01?) ? nnn alphanumeric traceability code ? pb-free jedec designator for matte tin (sn) ? * this package is pb-free. the pb-free jedec designator ( ) ? can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e RFPIC12F675 ds70091b-page 124 preliminary ? 2003-2013 microchip technology inc. package type: 20-lead ssop 20-lead plastic shrink small outline (ss) - 209 mil, 5.30 mm (ssop) 10 5 0 10 5 0 ? mold draft angle bottom 10 5 0 10 5 0 ? mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 ? foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 7.34 7.20 7.06 .289 .284 .278 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.18 7.85 7.59 .322 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 20 20 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c ? ? ? a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: mo-150 drawing no. c04-072 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2003-2013 microchip technology inc. preliminary ds70091b-page 125 RFPIC12F675 appendix a: data sheet revision history revision a this is a new data sheet. revision b added a note to each package outline drawing. RFPIC12F675 ds70091b-page 126 preliminary ? 2003-2013 microchip technology inc. notes: ? 2003-2013 microchip technology inc. preliminary ds70091b-page 127 RFPIC12F675 index a a/d ...................................................................................... 39 acquisition requirements ........................................... 43 block diagram............................................................. 39 calculating acquisition time....................................... 43 configuration and operation....................................... 39 effects of a reset ..................................................... 44 internal sampling switch (rss) impedance ................ 43 operation during sleep ............................................ 44 pic12f675 converter characteristics ...................... 106 source impedance...................................................... 43 summary of registers ................................................ 44 absolute maximum ratings ................................................ 87 ac characteristics industrial and extended .............................................. 99 additional pin functions ..................................................... 17 interrupt-on-change.................................................... 19 weak pull-up............................................................... 17 analog input connection considerations............................ 36 analog-to-digital converter. see a/d assembler mpasm assembler..................................................... 81 b block diagram tmr0/wdt prescaler................................................. 25 block diagrams analog input mode...................................................... 36 analog input model ..................................................... 43 comparator output ..................................................... 36 comparator voltage reference .................................. 37 gp0 and gp1 pins...................................................... 20 gp2............................................................................. 21 gp3............................................................................. 21 gp4............................................................................. 22 gp5............................................................................. 22 on-chip reset circuit ................................................. 59 rc oscillator mode..................................................... 58 timer1......................................................................... 28 watchdog timer.......................................................... 69 brown-out associated registers .................................................. 62 brown-out detect (bod) ..................................................... 61 brown-out detect timing and characteristics................... 102 c c compilers mplab c17 ................................................................ 82 mplab c18 ................................................................ 82 mplab c30 ................................................................ 82 calibrated internal rc frequencies.................................. 100 clkout ............................................................................. 58 code examples changing prescaler .................................................... 27 data eeprom read .................................................. 47 data eeprom write .................................................. 47 initializing gpio .......................................................... 17 saving status and w registers in ram ................. 68 write verify ................................................................. 47 code protection .................................................................. 69 comparator ......................................................................... 33 associated registers .................................................. 38 configuration............................................................... 35 effects of a reset ..................................................... 37 i/o operating modes................................................... 35 interrupts..................................................................... 38 operation.................................................................... 34 operation during sleep............................................ 37 output......................................................................... 36 reference ................................................................... 37 response time .......................................................... 37 comparator specifications................ 105, 108, 109, 110, 111 comparator voltage reference specifications................. 105 configuration bits ............................................................... 56 configuring the voltage reference..................................... 37 crystal operation................................................................ 57 crystal oscillator................................................................. 50 d data eeprom memory associated registers/bits........................................... 48 code protection.......................................................... 48 eeadr register......................................................... 45 eecon1 register ...................................................... 45 eecon2 register ...................................................... 45 eedata register....................................................... 45 data memory organization................................................... 5 dc characteristics extended and industrial.............................................. 96 industrial ..................................................................... 90 demonstration boards picdem 1................................................................... 84 picdem 17................................................................. 84 picdem 18r pic18c601/801 ................................... 85 picdem 2 plus........................................................... 84 picdem 3 pic16c92x............................................... 84 picdem 4................................................................... 84 picdem lin pic16c43x ........................................... 85 picdem usb pic16c7x5 ......................................... 85 picdem.net internet/ethernet.................................... 84 development support ......................................................... 81 device overview................................................................... 3 e eeprom data memory reading ...................................................................... 47 spurious write ............................................................ 47 write verify ................................................................. 47 writing ........................................................................ 47 electrical specifications ...................................................... 87 errata .................................................................................... 2 evaluation and programming tools.................................... 85 f firmware instructions ......................................................... 73 g general purpose register file ............................................. 5 gpio associated registers.................................................. 23 gpio port ........................................................................... 17 gpio, trisio registers..................................................... 17 i id locations........................................................................ 69 in-circuit debugger............................................................. 71 in-circuit serial programming............................................. 71 indirect addressing, indf and fsr registers ................... 16 instruction format............................................................... 73 instruction set..................................................................... 73 addlw....................................................................... 75 addwf ...................................................................... 75 andlw....................................................................... 75 andwf ...................................................................... 75 bcf ............................................................................ 75 RFPIC12F675 ds70091b-page 128 preliminary ? 2003-2013 microchip technology inc. bsf ............................................................................. 75 btfsc ........................................................................ 75 btfss ........................................................................ 75 call ........................................................................... 76 clrf........................................................................... 76 clrw ......................................................................... 76 clrwdt..................................................................... 76 comf ......................................................................... 76 decf .......................................................................... 76 decfsz...................................................................... 77 goto ......................................................................... 77 incf............................................................................ 77 incfsz ....................................................................... 77 iorlw ........................................................................ 77 iorwf ........................................................................ 77 movf.......................................................................... 78 movlw ...................................................................... 78 movwf ...................................................................... 78 nop ............................................................................ 78 retfie ....................................................................... 78 retlw ....................................................................... 78 return ..................................................................... 79 rlf ............................................................................. 79 rrf............................................................................. 79 sleep ........................................................................ 79 sublw ....................................................................... 79 subwf ....................................................................... 79 swapf ....................................................................... 80 xorlw....................................................................... 80 xorwf....................................................................... 80 summary table........................................................... 74 internal 4 mhz oscillator..................................................... 58 internal sampling switch (rss) impedance ........................ 43 interrupts ............................................................................. 65 a/d converter ............................................................. 67 comparator ................................................................. 67 context saving............................................................ 68 gp2/int ...................................................................... 67 gpio ........................................................................... 67 summary of registers ................................................ 68 tmr0 .......................................................................... 67 m mclr .................................................................................. 60 memory organization data eeprom memory.............................................. 45 mode control logic ............................................................. 54 mplab asm30 assembler, linker, librarian ..................... 82 mplab icd 2 in-circuit debugger...................................... 83 mplab ice 2000 high performance universal ? in-circuit emulator .............................................................. 83 mplab ice 4000 high performance universal ? in-circuit emulator .............................................................. 83 mplab integrated development environment ? software .............................................................................. 81 mplink object linker/mplib object librarian .................. 82 o opcode field descriptions ............................................... 73 oscillator configurations ..................................................... 57 oscillator start-up timer (ost) .......................................... 60 p package marking information ........................................... 123 packaging information ...................................................... 123 pcl and pclath ............................................................... 15 computed goto........................................................ 15 stack ........................................................................... 15 phase-locked loop (pll) .................................................. 53 pickit 1 flash starter kit.................................................. 85 picstart plus development programmer....................... 83 pin descriptions and diagrams .......................................... 20 power amplifier................................................................... 53 power control/status register (pcon).............................. 61 power select (table) .......................................................... 53 power-down mode (sleep) .............................................. 70 power-on reset (por)....................................................... 60 power-up timer (pwrt) .................................................... 60 prescaler............................................................................. 27 switching prescaler assignment ................................ 27 pro mate ii universal device programmer ..................... 83 program memory organization............................................. 5 programming, device instructions...................................... 73 r rc oscillator....................................................................... 58 read-modify-write operations ............................. 73 registers adcon0 (a/d control)............................................... 41 ansel (analog select) .............................................. 42 cmcon (comparator control) ................................... 33 config (configuration word) ................................... 56 eeadr (eeprom address) ...................................... 45 eecon1 (eeprom control) ..................................... 46 eedat (eeprom data) ............................................ 45 intcon (interrupt control)......................................... 11 iocb (interrupt-on-change gpio) ............................. 19 maps pic12f629 ........................................................... 6 pic12f675 ........................................................... 6 option_reg (option) ........................................ 10, 26 osccal (oscillator calibration) ................................ 14 pcon (power control) ............................................... 14 pie1 (peripheral interrupt enable 1)........................... 12 pir1 (peripheral interrupt 1)....................................... 13 status ....................................................................... 9 t1con (timer1 control) ............................................ 30 vrcon (voltage reference control) ......................... 38 wpu (weak pull-up)................................................... 18 reset................................................................................ 59 revision history................................................................ 125 s software simulator (mplab sim) ...................................... 82 software simulator (mplab sim30) .................................. 82 special features of the cpu .............................................. 55 special function registers ................................................... 6 special functions registers summary................................. 7 t time-out sequence ............................................................ 61 timer0................................................................................. 25 associated registers .................................................. 27 external clock............................................................. 26 interrupt ...................................................................... 25 operation .................................................................... 25 t0cki ......................................................................... 26 timer1 associated registers .................................................. 31 asynchronous counter mode ..................................... 31 reading and writing ........................................... 31 interrupt ...................................................................... 29 modes of operations .................................................. 29 operation during sleep............................................ 31 oscillator..................................................................... 31 prescaler .................................................................... 29 ? 2003-2013 microchip technology inc. preliminary ds70091b-page 129 RFPIC12F675 timer1 module with gate control ....................................... 28 timing diagrams clkout and i/o....................................................... 101 external clock............................................................. 99 int pin interrupt.......................................................... 67 pic12f675 a/d conversion (normal mode)............. 107 pic12f675 a/d conversion timing ? (sleep mode) .......................................................... 108 reset, watchdog timer, oscillator start-up ? timer and power-up timer ....................................... 102 time-out sequence on power-up (mclr not tied to v dd )/ case 1 ................................................................ 64 case 2 ................................................................ 64 time-out sequence on power-up (mclr tied ? to v dd ) ........................................................................ 64 timer0 and timer1 external clock ........................... 104 timer1 incrementing edge.......................................... 29 timing parameter symbology............................................. 98 u uhf ask/fsk transmitter cept .......................................................................... 49 fcc............................................................................. 49 radio frequency......................................................... 49 transmitter.................................................................. 49 v voltage reference accuracy/error ..................................... 37 w watchdog timer summary of registers ................................................ 69 watchdog timer (wdt) ...................................................... 68 www, on-line support ....................................................... 2 RFPIC12F675 ds70091b-page 130 preliminary ? 2003-2013 microchip technology inc. notes: ? 2003-2013 microchip technology inc. ds70091b-page 131 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support ds70091b-page 132 ? 2003-2013 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds70091b 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? ? 2003-2013 microchip technology inc. preliminary ds70091b-page 133 RFPIC12F675 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . * jw devices are uv erasable and can be programmed to any device configuration. jw devices meet the electrical requirement of each oscillator type. sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip worldwide site (www.microchip.com) part no. x /xx xxx pattern package temperature range device device : standard v dd range t: (tape and reel) temperature range i = -40 ? c to +85 ? c e= -40 ? c to +125 ? c package ss = ssop pattern 3-digit pattern code for qtp (blank otherwise) examples: a) rf pic12f675 f ? e/ss 301 = extended temp., ssop package, 434 mhz, qtp pattern #301 b) RFPIC12F675fht ? i/ss = industrial temp., ssop package, 868 mhz, tape and reel RFPIC12F675 ds70091b-page 134 preliminary ? 2003-2013 microchip technology inc. ? 2003-2013 microchip technology inc. preliminary ds70091b-page 135 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, application maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2003-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620769683 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification contained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outsi de the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improving the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == ds70091b-page 136 preliminary ? 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